JP2001235567A - Logical slowing/quickening device, electronically controlled mechanical timepiece and logical slowing/ quickening method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical slowing/quickening device capable of executing normal logical slowing/quickening processing even when driving voltage is lowered. SOLUTION: This logical slowing/quickening device 100 is provided with a signal delay absorbing circuit 160 for absorbing a delay of a logical slowing/ quickening timing signal used for the formation of a start control signal, relative to a source oscillation signal. Since the signal delay absorbing circuit 160 eliminates the delay of the logical slowing/quickening timing signal FVCW relative to the source oscillation signal, even when the driving voltage of an IC is lowered, the start control signal VCW can be positively formed to realize normal logical slowing/quickening processing. Since the normal logical slowing/ quickening processing can be executed even when the driving voltage is lowered, the duration of a timepiece can be extended by that portion, and energy saving is also attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical accelerating / decreasing device for correcting a deviation from an absolute time of a time reference signal in a clock IC or the like, and an electronically controlled mechanical timepiece equipped with the logical accelerating / decreasing device.

[0002]

2. Description of the Related Art In a conventional timepiece IC or the like, in order to correct a deviation from an absolute time of a time reference signal output from an oscillation circuit, a time reference signal or a frequency-divided signal as a basic signal is corrected at a predetermined correction period. A digital acceleration / deceleration method that expands and contracts by a necessary correction amount (acceleration / reduction amount) every (deceleration / reduction cycle) is adopted.

[0003] As this conventional digital acceleration / deceleration system, the one disclosed in the prior art of Japanese Patent Application Laid-Open No. 6-27265 is known. That is, FIG. 10 shows a logical regulation circuit employing a conventional digital regulation system. This FIG.
Is a oscillating circuit 10 oscillating at 32 KHz as a source oscillation, a variable frequency dividing circuit 20 composed of 1/2 frequency dividers 22, 24 and 26 with a data set function, and a time dividing circuit from the variable frequency dividing circuit 20. frequency divider 30 to obtain the reference signal S _T
When a regulation period generating circuit 40 for generating a pace periodic signal S _F based on a signal of the frequency divider circuit 30, and the pace periodic signal S _F 32
A slow / fast execution timing signal forming circuit 5 for generating a slow / fast execution timing signal VCW from the KHz source oscillation clock f ₀
0, a correction data supply means 60 for supplying, for example, 3-bit correction data, and a frequency division ratio for transmitting the correction data to the set input S of the 1/2 frequency dividers 22, 24, 26 by generation of the slow / slow execution timing signal VCW. And a setting circuit 70.

The slow / slow execution timing signal forming circuit 50
When the clock input CL is at a high level (hereinafter referred to as "H"), the slow / fast period signal S _F is transmitted as a data input D to the inverted output XM, and when the clock input CL is at a low level (hereinafter referred to as "L"). a latch 52 to maintain the inverted output XM, and a NOR gate 54 for outputting a pace execution timing signal VCW the regulation period signal S _F and the inverted output XM as input. The frequency division ratio setting circuit 70 includes AND gates 72, 74, and 76.

Normally, the cycle T of the slow / fast cycle signal S _F is a relatively long cycle of several seconds to several hundred seconds. Slow / fast cycle signal S
Since _F are those obtained by dividing the divided output of the 1/2 frequency divider 26 (4 KHz) in the frequency divider circuit 30, as shown in FIG. 11, regulation period signal S _F from "H" When changing to "L", 32KHz, 16KHz, 8KHz, 4KH
All signals of z are in the state of “L”. Immediately before this falling point, the slow / fast cycle signal S _F is “H”.
Since the source clock f ₀ as the clock input CL is also “H”, the inverted output XM of the latch 52 is “L”.
It is. The regulation period signal S _F is rising transition from "H" to "L", the period t / 2 source clock f ₀ is "L" (1/2 cycle), inverting the output XM is at the "L" Since it is held as it is, the slow / slow execution timing signal VCW of “H” is generated over the period t / 2.

Here, the slow / slow execution timing signal VCW is
"H", for example, when the correction data (CBA) is (01)
If 1), the variable frequency dividing circuit 2 in this period t / 2
The contents of 0 are set to the state of point P. Also for example correction
If the data (CBA) is (111), this period t /
2, the content of the variable frequency dividing circuit 20 is set to the state of the point Q.
Is Therefore, the variable frequency dividing circuit 20 is set at the point P.
The period reference signal S _T Is the acceleration / deceleration amount T_P = (1 / 32K
Hz) × 3 = 92 μsec shorter than the slow / fast cycle
The variable frequency dividing circuit 20 is set at the point Q.
Then, the period reference signal S_T Is the acceleration / deceleration amount T_Q = (1 / 32KH
z) × 7 = 214 μsec shorter than the slow / fast cycle
Will be. In this example, 3 bits are used for easy explanation.
The correction data is actually
It becomes positive data, in which case the maximum amount of slowdown is 0.98 μs
ec.

In the case of a timepiece IC, a power source having a smaller output than a battery other than a battery, such as a solar battery or a rotating weight, or a battery such as a generator rotated by a mainspring, is used to extend the life of the battery. But the power has been reduced so that it can operate. Therefore, the power consumption for operating the timepiece IC is reduced to a low voltage (for example, about 0.5 V), thereby reducing current consumption and realizing energy saving.

[0008]

However, when the driving voltage is reduced in the logic acceleration / reduction device, the energy of each signal is also reduced, and the response of the circuit is deteriorated, resulting in a problem that the signal delay becomes remarkable. .

That is, in the conventional logic moderator, when the drive voltage decreases, the source oscillation signal is divided into the frequency dividers 22 and 2.
As the frequency is divided by the frequency dividers 4, 26 and the frequency dividing circuit 30 sequentially, the frequency-divided signal is delayed with respect to the source signal, and the delay is integrated. Therefore, in particular, the signal from the slow / fast period frequency dividing circuit 30, which is the final signal of the frequency divider,
There is a problem that the signal delay becomes very noticeable.

When the signal delay increases, a slow-fast cycle signal S _F formed based on the signal from slow-fast cycle dividing circuit 30 also has a delay. In the timing chart shown in FIG. a falling edge timing of the signal S _F has been deviated to the right side in FIG.
For this reason, when the pulse width of the slow / fast execution timing signal VCW becomes extremely small, or when the above-mentioned timing, that is, when the signals of 32 KHz, 16 KHz, 8 KHz, and 4 KHz are all in the “L” state, the slow / fast execution timing signal VCW is output. However, there is a problem that normal logical acceleration / deceleration processing cannot be executed due to these. For example, when the pulse width of the slow / fast execution timing signal VCW is about 15.3 μsec (= 1 / (32768 × 2)), the time until the signal change of the source vibration (32 KHz) is transmitted to the slow / fast cycle generating circuit 40 If the (signal delay time) becomes equal to or greater than the pulse width (about 15.3 μsec) of the slow / fast execution timing signal VCW, it becomes impossible to form a logic slow / fast pulse (start control signal), and the logic slow / fast processing cannot be executed. There was a problem.

Here, as shown in FIG. 12, power supplied from a secondary power supply such as a battery or a capacitor having a voltage VSS is usually changed to a voltage Vreg (which varies slightly depending on temperature,
(About 0.65 to 0.55 V). As long as the voltage Vreg is secured, the logical acceleration / deceleration process also operates normally.

However, if the drive voltage drops below Vreg and falls below the voltage V (a voltage that can be processed slowly), there is a problem that normal logical acceleration / deceleration processing cannot be performed. At this time, a battery type timepiece that drives a hand by driving a step motor with a normal battery, a rotating weight type generator, and a secondary battery type that drives a hand by driving a step motor with a secondary battery charged by a solar battery or the like. In the timepiece, the hand movement is stopped or the operation of the IC is stopped before the drive voltage becomes equal to or lower than Vreg. Therefore, there is no problem even if the normal logical regulation processing is not performed when the drive voltage is equal to or lower than Vreg.

On the other hand, as described in Japanese Patent Publication No. Hei 7-119812, mechanical energy when the mainspring is opened is converted into electric energy by a generator, and the rotation control device is operated by the electric energy. There is known an electronically controlled mechanical timepiece that controls a current value flowing through a coil of a generator to accurately drive a pointer fixed to a wheel train and accurately display time.

In this electronically controlled mechanical timepiece, the hands themselves are driven by the mainspring, so that the mainspring is released and the mechanical energy is reduced, and the driving voltage generated by the generator is Vreg.
The hand movement will continue even if it falls below. Therefore, the electronically controlled mechanical timepiece must perform a normal logical acceleration / deceleration process until the voltage Vstop at which the IC stops even if the drive voltage becomes such a low drive voltage. However, as described above, there is a problem that normal processing cannot be performed due to signal delay at such a low driving voltage.

If the normal logical acceleration / deceleration processing cannot be performed in this way, there is a problem that a rate deviation occurs and a time error occurs.

It is an object of the present invention to provide a logic acceleration / reduction device and an electronically controlled mechanical timepiece capable of performing normal logic acceleration / deceleration processing even when the drive voltage is reduced.

[0017]

According to the present invention, there is provided a logical acceleration / deceleration device which executes a predetermined amount of acceleration / deceleration operation by a start control signal with respect to a time reference signal generated based on a source vibration signal from an oscillating means. In a logic acceleration / reduction device having an amount providing means, a signal delay absorption circuit for absorbing a delay of a logic acceleration / deceleration timing signal used for forming the activation control signal with respect to the source signal is provided. .

In the present invention, the delay of the logical timing signal with respect to the source signal is eliminated by the signal delay absorption circuit. Therefore, even when the driving voltage of the IC is reduced and the energy of the signal is reduced, it is possible to reduce the energy of the signal. , The start control signal can be formed reliably, and normal logical acceleration / deceleration processing can be performed. Then, even if the drive voltage is reduced, normal logic acceleration / deceleration processing can be performed, so that the duration of the clock can be extended correspondingly and energy saving can be achieved.

Here, a frequency dividing circuit having a plurality of frequency dividers for frequency dividing the source oscillation signal from the oscillating means as the speed increasing / decreasing means, and using the signal from the frequency dividing circuit, the logic speed increasing / decreasing means. A logic slow / fast timing signal forming circuit for forming a timing signal; a start control signal forming circuit for forming the start control signal based on an output signal from the signal delay absorbing circuit; and a set state or reset of the plurality of frequency dividers A slow / fast amount setting device that sets a state to allow adjustment of a predetermined slow / fast amount, a frequency divider circuit control circuit that sets or resets a frequency divider circuit set by the slow / fast amount setting device by the activation control signal. And the like can be used.

In addition, the signal delay absorbing circuit includes a pre-change signal that generates a pre-change signal that changes a predetermined time before a time when the activation control signal is originally generated when the logical acceleration / deceleration timing signal is in an active state. A generating circuit;
And a change timing synchronizing circuit that adjusts a change timing of the output signal to a time when the activation control signal is originally generated based on the pre-change signal output from the pre-change signal generation circuit. .

According to the present invention, a pre-change signal is generated by a pre-change signal generating circuit, and the signal is changed to an original change timing by a change timing synchronizing circuit. , The change timing synchronization circuit can be surely adjusted to a predetermined timing. And
Since the pre-change signal is created and then synchronized by the change timing synchronization circuit, even if the delay amount included in the pre-change signal has a wide range, it can be synchronized by the change timing synchronization circuit, and the characteristics of the oscillation circuit and Even when the delay amount differs depending on the value of the drive voltage, the difference can be absorbed and the change timing can be synchronized.

At this time, the change timing synchronization circuit has a data input terminal to which a pre-change signal from the pre-change signal generation circuit is input, and a clock input to which a low-delay signal having a small delay with respect to the source signal is input. The flip-flop preferably includes a terminal.

In the present invention, the change of the pre-change signal input to the flip-flop is output from the flip-flop in synchronization with the low-delay signal input to the clock input terminal. More specifically, the output of the flip-flop is output with a delay of one cycle of the low-delay signal (one cycle in the case of one flip-flop) with respect to the change of the pre-change signal. The timing is output in synchronization with the cycle of the low delay signal. Therefore, if the pre-change signal generation circuit is set so that the pre-change signal changes timing one cycle before the low-delay signal with respect to the original timing, the output of the flip-flop will be It is output at the original change timing in synchronization with a low-delay signal having no or small delay.

For this reason, even if the pre-change signal is delayed compared to the source signal, the output of the flip-flop changes in synchronization with a low-delay signal having no or small delay with respect to the source signal. Therefore, the output change of the flip-flop with respect to the source signal changes little with respect to the fluctuation period of the source signal, that is, changes in synchronization with the source signal,
The start control signal can be reliably formed, and the logical acceleration / deceleration process can be reliably performed.

[0025] Further, the acceleration / deceleration amount providing means includes a frequency dividing circuit including a plurality of frequency dividers for dividing the frequency of the source oscillation signal from the oscillating means, and the low delay signal is a source oscillation signal or the frequency dividing signal. It is preferably a frequency-divided signal output from the first or second frequency divider of the circuit.

In this case, even if the energy of each signal is reduced by driving with a low voltage such as a clock IC or the like, the low delay signal input to the clock input of the flip-flop is changed to the source oscillation signal itself or the source oscillation signal. If the output signal of the first or second stage of the frequency divider circuit that divides the oscillation signal is used, there is no delay with respect to the source oscillation signal, or the delay can be made very small, and the logical acceleration / deceleration processing can be performed more reliably. It can be carried out.

That is, in the present invention, a low-delay signal means a signal having no delay with respect to the source vibration signal,
Any signal that can form the start control signal even with a delay, specifically, a signal whose delay time is shorter than the pulse width of the start control signal may be used.

Also, an electronically controlled mechanical timepiece according to the present invention comprises a mechanical energy source, a generator driven by the mechanical energy source to generate induced power and supply electrical energy, An electronically controlled mechanical timepiece comprising: a rotation control device driven by the motor to control the rotation cycle of the generator; and a time display device rotated together with the generator by the mechanical energy source and controlled by the rotation control device. Wherein the rotation control device includes the logical acceleration / deceleration device.

According to the present invention, by using a logic acceleration / deceleration device having a signal delay absorption circuit, normal logic acceleration / deceleration processing can be performed even when the driving voltage of the IC decreases and the signal energy decreases. Can be. For this reason, in an electronically controlled mechanical timepiece that continues to move hands even when the drive voltage decreases, a time error can be prevented and the duration of the timepiece can be extended.

Further, the logic acceleration / deceleration method of the present invention is a logic acceleration / deceleration method for executing a predetermined acceleration / deceleration operation by a start / stop signal with respect to a time reference signal generated based on a source signal from an oscillating means. Absorbing a delay of the logical acceleration / deceleration timing signal used to form the start control signal with respect to the source signal, and forming the start control signal based on the signal in which the delay has been absorbed. Things.

In the present invention as well, since the delay of the logical acceleration / deceleration timing signal with respect to the source oscillation signal is absorbed and eliminated, even when the IC driving voltage is reduced and the signal energy is reduced, the start-up is performed. The control signal can be reliably formed, and normal logical acceleration / deceleration processing can be performed. Then, even if the drive voltage is reduced, normal logical acceleration / deceleration processing can be performed, so that the duration of the clock can be extended correspondingly, and energy saving can be achieved.

[0032]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of an electronically controlled mechanical timepiece according to an embodiment of the present invention.

The electronically controlled mechanical timepiece is connected to a mainspring 201 a as a mechanical energy source, a speed increasing wheel train 207 as an energy transmission device for transmitting the torque of the main spring 201 a to the generator 220, and connected to the speed increasing wheel train 207. Hands (minute hand, second hand, hour hand)
213.

The generator 220 is driven by the mainspring 201a through the speed increasing wheel train 207, generates induced power, and supplies electric energy. The AC output from the generator 220 is boosted and rectified through a rectification circuit 241 including step-up rectification, full-wave rectification, half-wave rectification, transistor rectification, and the like, and is supplied to a power supply circuit 240 including a capacitor and the like.

The rotation control device 250 is driven by the electric power supplied from the power supply circuit 240, and the speed control of the generator 220 is controlled by the rotation control device 250. The rotation control device 250 includes the oscillation circuit 110, the frequency divider 13
0, a rotor rotation detection circuit 253, a brake control circuit 255, and a logical acceleration / deceleration device 100. The speed of the generator 220 is controlled by controlling a brake circuit provided in the generator 220. .

The brake circuit is connected to the generator 220
And the like, in which each terminal is closed in a closed loop state by a short circuit or the like and a short brake is applied.

The oscillation circuit 110 uses a quartz oscillator 110A, which is a time standard source, to generate a source vibration of 32 kHz (3276).
8 Hz), and the oscillation signal is frequency-divided by a frequency dividing circuit 130 including a plurality of frequency dividers (for example, 15-stage flip-flops) up to a certain period. The output of the twelfth stage of the frequency divider 130 is output as the 8 Hz reference signal fs.

The rotation detecting circuit 253 includes a waveform shaping circuit connected to the generator 220, a monomultivibrator, and the like, converts a sine wave output from the generator 220 into a rectangular wave, and further converts the sine wave into a rectangular wave. And outputs the rotation detection signal FG1 from which noise has been removed.

The braking control circuit 255 is connected to the reference signal fs
And the rotation detection signal FG1, and the brake amount is set based on the phase difference between the signals and the like, so that the speed of the generator 220 can be adjusted. FIG. 2 is a block diagram showing the configuration of the logic moderator 100, and FIG. 3 is a circuit block diagram showing the circuit configuration.

The logic moderator 100 includes a timer 1 for counting the output from the frequency divider 130 having a plurality of frequency dividers 131 for sequentially dividing the frequency of the oscillation signal from the oscillation circuit 110.
40, a logic slow / fast timing pulse forming circuit 150 for forming a fast / fast timing pulse (FVCW) based on a signal from the timer 140, and a signal delay absorbing circuit for outputting a signal QQQ having no or small delay with respect to the source signal 160 and a logic slow / fast pulse V which is an activation control signal based on the output signal QQQ from the signal delay absorption circuit 160.
A logical slow / fast pulse forming circuit 170 for forming CW and a frequency dividing circuit SET / RESET which is a frequency dividing circuit control circuit for setting a predetermined frequency divider 131 of the frequency dividing circuit 130 to a set state or a reset state based on the logical slow / fast pulse VCW. The circuit is provided with a slow / fast amount providing unit including a circuit 180 and a slow / fast amount setting device 190 for setting a slow / fast amount by the frequency dividing circuit SET / RESET circuit 180.

Each frequency divider 131 of the frequency dividing circuit 130 is configured to divide a clock input signal by a frequency (1/2) and output the signal from an output terminal Q. Therefore, each divider 131
Is connected in series as the clock input CL of the next frequency divider 131, so that 32 KHz (32768 Hz) → 16
KHz (16384Hz) → 8KHz (8192Hz) → 4KHz (4096H
z) → 2KHz (2048Hz) → 1KHz (1024Hz) → 512Hz
→ ... 1 Hz and frequency-divided the source vibration signal sequentially, and finally 1H
It is configured to output a signal of z.

Each frequency divider 131 has a set terminal S
And a reset terminal R. When an H level signal is input to the set terminal S, the output Q is forcibly set to an H level signal. When an H level signal is input to the reset terminal R, The output Q is forcibly set to an L level signal. Further, as shown in the timing charts of FIGS. 4 to 6, the frequency divider 131 which outputs the frequency-divided signal F2K of 2 kHz outputs a signal F2KM obtained by advancing the frequency-divided signal of 2 kHz by 1/4 cycle. A terminal M is provided. The frequency divider 131 that outputs the frequency-divided signal F1K of 1 KHz is provided with a terminal XM that outputs a signal XF1KM obtained by advancing the frequency-divided signal of 1 KHz by ４ period and inverting the signal XF1KM.

The timer 140 is configured to be able to count a set time using an output signal (1 Hz in the present embodiment) from the frequency dividing circuit 130. More specifically, in the present embodiment, the timer 140 is set as a 10-second timer.
When seconds are counted, a signal is output to the logic timing pulse forming circuit 150.

The logic slow / fast timing pulse forming circuit 150
Becomes active (H level) at a timing of every 10 seconds based on the output signal from the timer 140.
As shown in the timing chart of FIG. 6, it is configured to output a logic slow / fast timing pulse (FVCW).

The logic timing pulse (FVCW)
Are input to the signal delay absorption circuit 160. The signal delay absorption circuit 160 includes a pre-change signal generation circuit 165,
And a change timing synchronization circuit 161.

The pre-change signal generation circuit 165 includes an OR gate 166 and NAND gates 167 and 168. The OR gate 166 is connected to the signal F2KM.
And the signal XF1KM to output a logical sum signal B. NA
The logical sum signal B and the output C of the NAND gate 168 are input to the ND gate 167. The output of the NAND gate 167 is a logical slow / fast timing pulse (FV
CW), and input to the NAND gate 168,
AND gate 168 is configured to output pre-change signal C.

The change timing synchronizing circuit 161 is a flip-flop which receives the pre-change signal C as a data input, and receives, as a clock input, an 8 kHz signal TTT which is an output of the frequency divider 131 at the second stage from the source signal. It is constituted by. Therefore, the change timing synchronization circuit 161
As described in each timing chart, a signal QQQ obtained by changing the change of the pre-change signal C in synchronization with a signal of 8 KHz is output.

The logic slow / fast pulse forming circuit 170 receives the output signal QQQ from the change timing synchronizing circuit 161 of the signal delay absorbing circuit 160 and the signal of the source oscillation signal 32 KHz, and is a one-shot having a width corresponding to a half cycle of 32 KHz. A pulse is formed, and a logic slow / fast pulse VCW which is a start control signal
It is configured to output as. Specifically, a signal E is formed by using the output signal QQQ and the source signal A, and the signal E and the signal QQQ are input to a NOR gate to form a logic slow / fast pulse (VCW).

As shown in FIGS. 4 to 6, the signal TTT input to the change timing synchronization circuit 161 and the signal A input to the logic slow / fast pulse forming circuit 170 have a logic slow / fast timing pulse (FVCW). It is set so that only the H level signal is input to each of the circuits 161 and 170, thereby reducing power consumption as compared with the case where each signal is constantly input. Specifically, 32K
Hz source oscillation signal and logic timing pulse (FVC
W) is input, and an AND gate 172 to which an 8 KHz signal and a logic slow / fast timing pulse (FVCW) are input is provided.
The output of the gates 171 and 172 may be the signal A or the signal TTT.

The frequency dividing circuit SET / RESET circuit 180 is composed of five AND gates 181. Each AND
The gate 181 has a logic slow / fast pulse (VCW) from the logic slow / fast pulse forming circuit 170 and a slow / fast amount setting device 190.
And an H level signal or an L level signal.

Of these AND gates 181, 4
The AND signal of the AND gates 181 is
The first to fourth frequency dividers 13 counted from the 0 oscillation circuit 110
1 is input to the set terminal S. Also, the remaining AN
The logical product signal of the D gate 181 is output to the fifth-stage frequency divider 131.
Is input to the reset terminal R.

The logic slow / fast pulse (VCW) from the logic slow / fast pulse forming circuit 170 is input to the reset terminal R of the sixth-stage frequency divider 131. This is 5
When the frequency divider 131 at the stage outputs an H level signal, the frequency change signal of the sixth stage frequency divider 131 is changed from the L level signal to the H level signal by a signal change at the time of forced reset. In order not to change.

The acceleration / deceleration amount setting device 190 includes an AND gate 1
81 are provided with five terminals L1 to L5.
Each of the terminals L1 to L5 is connected to the power supply voltage VDD, and is configured to input an H level signal to each of the AND gates 181. Also, the terminals L1 to L5 are
It is grounded via a pull-down resistor 191, and is punched at a punched portion 192 of the circuit board to supply a power supply voltage VDD.
Is disconnected, the L level signal is input to each AND gate 181.

Next, the operation of the present embodiment having such a configuration will be described with reference to the timing charts of FIGS. 4 to 6 and the flowchart of FIG.

First, the characteristics of the individual oscillation circuits 110 (crystal oscillators) are inspected in advance, and the amount of acceleration / deceleration corresponding to each oscillation circuit 110 is set by the acceleration / deceleration amount setting device 190. In particular,
By appropriately punching out the punching portions 192 corresponding to the terminals L1 to L5, the amount of acceleration / deceleration corresponding to each oscillation circuit 110 is set in advance. In the present embodiment, five terminals L1 to L5
And 5 bits, that is, 32 kinds of adjustments are possible. Each of the terminals L1 to L5 is referred to as "1" (a state in which an H level signal is input to the AND gate 181 because the punched portion 192 connected to the terminal is not punched and the voltage VDD is applied to the terminal). , "0" (the punched portion 192 connected to the terminal is punched, and the terminal is opened or the terminal is supplied with the voltage Vreg or the voltage VSS lower than the voltage VDD. Tables 1 and 2 below show the correction amounts when the L level signal is set to the input state.

[0056]

[Table 1]

[0057]

[Table 2]

Since the present embodiment is a 5-bit logical acceleration / deceleration device, as shown in FIG. 4, the half cycle of the signal F16K is one step, and all the signals F16K to F1K are L level signals. Signal F16
The amount of acceleration / deceleration can be adjusted in 32 steps until all the signals from K to F1K are H level signals.

In order to expand and contract the amount of acceleration / deceleration, first, a logical acceleration / deceleration pulse (VCW) is applied to the central part of 32 steps (the ninth cycle of the signal F16K, ie, the signals F16K to F2).
K is set to the L level signal and the signal F1K is set to the H level signal (at the time when it is set to the H level signal), and the state is set to 0 step. In addition, the state at the time when the logical acceleration / deceleration pulse (VCW) is input is changed to the state immediately before (the left side in each timing chart) (signals F16K to F2).
K is “H” and the signal F1K is “L”).
1 "step, one state ahead (right side in each timing chart) (signals F16K to F2K are" L "and signal F1
The setting for K to be "F") is a "+1" step, and the other steps are set in a similar manner.

Note that the logical slow / fast pulse (VCW) is input at the time when the signals F16K to F2K are L level signals and the signal F1K is H level signals, so that the signals F16K to F2K are set to H level. In the steps that need to be performed, the corresponding terminals L1 to L4 are set to “1” (wiring 1
93 is not punched out), and an H level signal is applied to the set terminal S of the frequency divider 131. On the other hand, in the step in which the signals F16K to F2K need to be set to the L level, the signal is not input to the set terminal S, that is, the corresponding terminals L1 to L4 are set to “0” (wiring 193 is punched out).

Similarly, in a step in which signal F1K needs to be set to L level, corresponding terminal L5 is set to "1".
(The state in which the wiring 193 is not punched) as the frequency divider 131
H level signal is applied to the reset terminal R. On the other hand, in the step where the signal F1K needs to be set to the H level, the signal F1K may be maintained at the H state.
No input is made to the reset terminal R, that is, the corresponding terminal L is set to “0” (the state where the wiring 193 is punched out).

In this embodiment, since the half cycle of the signal F16K is one step, and the acceleration / deceleration processing is performed at a cycle of 10 seconds, 0.264 (sec / sec) is performed for each step.
Sun) can be corrected. For this reason, in the case of step -16 (L1 to L4 are “0” and L5 is “1”), 16 steps (ie, 4.
224 seconds / day) set to be delayed, step +15
When (L1 to L4 are "1" and L5 is "0"), it is set so as to advance by 15 steps (that is, 3.96 seconds / day) as compared with the initial state.

When the amount of acceleration and deceleration is set in advance in this way,
In operation, the logic slow / fast pulse (VCW) is normally L
Since this is a level signal, an L level signal is input to the set terminal and reset terminal of each frequency divider 131. Therefore, each frequency divider 131 sequentially divides the frequency of the source oscillation signal and outputs the divided frequency without being forcibly set or reset.

When the operation is started, the frequency dividing circuit 130 outputs 1H
When the signal of z is output, the 10-second timer 140 starts (Step 1, hereinafter, step is abbreviated as “S”),
This 1 Hz output is counted by the timer 140.
When 10 seconds have elapsed by the timer 140 (S2), the signal from the timer 140 causes the logical slow / fast timing pulse forming circuit 150 to be activated (H level) at 10-second intervals. ) Is output (S3).

When the logic slow / fast timing pulse (FVCW) goes to H level, the pre-change signal generation circuit 165 outputs the pre-change signal C to the change timing synchronization circuit 16.
1 is input. Here, the pre-change signal C is formed using a signal F2KM, a signal XF1KM, and the like.
These signals are obtained by dividing the frequency divider 13 of the fourth and fifth stages from the source oscillation signal.
1, when the driving voltage of the frequency divider 130 is low, the delay in each frequency divider 131 is accumulated and the signal C
Is a large delay (for example, about 15.3 μ
sec or more).

This signal C is supplied to the change timing synchronization circuit 1
The change timing is output as a signal QQQ in synchronization with a signal F8K which is a low-delay signal having a small delay.

That is, the signal C changes from the H level to the L level every 10 seconds by the logic slow / fast timing pulse (FVCW). However, since this signal F2KM and the signal XF1KM include a delay, the change timing is delayed by more than a half cycle with respect to the source vibration signal.

On the other hand, the pre-change signal generation circuit 165
From the point in time when the logic slow / fast timing pulse (FVCW) changes to active (H level signal), the signal F8K
The signal C is set to change from the H level to the L level after the elapse of the cycle, and after one cycle, that is, from the time when the logic slow / fast timing pulse (FVCW) changes from “H” to “L”, After the elapse of four cycles of F8K, the signal Q
QQ is set to change from “H” to “L”. At this time, the output QQQ from the change timing synchronizing circuit 161 has almost no delay with respect to the source oscillation signal for the synchronized low-delay signal (8 KHz). It disappears, and the signal delay is absorbed (S4). In the change timing synchronizing circuit 161, when the signal C is delayed by one cycle or more of the low-delay signal, the signal QQQ cannot be changed at the above timing. Therefore, the signal QQQ can be surely changed at the above timing.

The logic slow / fast pulse forming circuit 17
At 0, the signal QQ having almost no delay with respect to the source vibration signal
Since Q is used, a logical slow / fast pulse (VCW) can be output reliably (S5).

At 10-second intervals, logic slow / fast pulses (VCW)
Is output (S5), the setting data in the acceleration / deceleration amount setting device 190 is read (S6), and the set terminal S and the reset terminal R of each frequency divider 131 are appropriately set to H according to this setting.
A level signal is input (S7), and each frequency divider 131 to which the H level signal is input is forcibly set (H level) or reset (L level).

For example, each terminal L of the acceleration / deceleration amount setting device 190
In the initial state where all of 1 to L5 are set to “0”,
As shown in the timing chart of FIG.
Is processed. Further, in the case of “−1 step” in which all the terminals L1 to L5 of the acceleration / deceleration amount setting device 190 are “1”, a logical acceleration / deceleration pulse (VCW) is input as shown in the timing chart of FIG. Time is 1
The state before the step is reached, and the delay direction is corrected.
Similarly, in the case of “−16 steps” in which the terminals L1 to L4 of the acceleration / deceleration amount setting device 190 are “0” and L5 is “1”, as shown in the timing chart of FIG. The time when (VCW) is input is the state 16 steps before, and the delay direction is corrected.

Further, although not shown, the acceleration / deceleration amount setting device 1
When each of the terminals L1 to L4 of the 90 is set to "+1 to +15 steps", the point in time when the logic slow / fast pulse (VCW) is input is 1 to 15 steps ahead, and the forward direction is corrected. You.

According to the present embodiment, the following effects can be obtained.

1) Since the signal delay absorbing circuit 160 is newly provided, the change timing of the signal QQQ input to the logical slow / fast pulse forming circuit 170 can be generated with almost no delay with respect to the source oscillation signal. Therefore, I
Even if the drive voltage such as C becomes low and the energy of each signal becomes small, the logic slow / fast pulse forming circuit 170 can surely form the logic slow / fast pulse (VCW), thereby ensuring the normal logic slow / fast operation. It can be executed and the rate deviation can be prevented.

2) Even if the voltage becomes low, time deviation can be prevented and accurate hand movement control can be performed. Therefore, the output voltage of the battery or the generator is lowered, so that the hand movement has to be stopped conventionally. Hand operation can be continued even in this state. For example, in the graph shown in FIG. 12, conventionally, normal operation could only be performed up to the level of the voltage V, but
According to the present embodiment, it is possible to perform a normal logical acceleration / deceleration process until the voltage drops to the level of the voltage Vstop.
The duration of the system can be extended by as much as 10-20%. In particular, in an electronically controlled mechanical timepiece in which the hands 213 are rotated by a mechanical energy source such as the mainspring 201a, even when the mainspring 201a is released, the output torque decreases, and the electromotive voltage of the generator 220 drops below Vreg. Since normal logical acceleration / deceleration processing can be performed, accurate hand movement without a deviation in the rate can be continued until the IC stops, and the duration can be effectively extended accordingly.

3) Since accurate hand movement control can be performed even at a low voltage, energy saving can be achieved. In particular, in a device such as a wristwatch driven by a secondary power source such as a battery or a generator, energy saving can be achieved, so that the duration can be extended, and the size and weight of the device can be reduced. Useful for

4) The signal delay absorption circuit 160 is replaced with the pre-change signal generation circuit 165 and the change timing synchronization circuit 16
1, even if the pre-change signal C that changes before the original change timing includes a delay, the change timing synchronizing circuit 161 can reliably match the predetermined timing. Since the pre-change signal C is created and then synchronized by the change timing synchronization circuit 161, the change timing synchronization circuit 161 can synchronize even if the delay amount included in the pre-change signal C has a wide range. Even when the delay amount differs depending on the characteristics of the oscillation circuit 110 and the value of the driving voltage, the difference can be absorbed and the change timing can be synchronized.

Note that the present invention is not limited to the above-described embodiment, but includes other configurations capable of achieving the object of the present invention, and the following modified examples are also included in the present invention.

For example, as the frequency dividing circuit SET / RESET circuit 180, as shown in FIG. 8, a wiring 183 capable of inputting the output of each AND gate 181 to both the set terminal and reset terminal of each frequency divider 131 , 184, and a select switch 185 for switching the connection between the output of each AND gate 181 and each of the wirings 183, 184, and the amount of change may be set by appropriately switching the connection between these select switches 185. As described above, if a setting is made such that a signal is always input to one of the set terminal and the reset terminal of each frequency divider 131 when the logic slow / fast pulse (VCW) is input, the operation of each frequency divider 131 can be improved. It can be controlled reliably and can be operated reliably.

In the above-mentioned embodiment, a switch may be provided at the punched portion 192, and the switch may be used to connect or disconnect the wiring, thereby setting the amount of acceleration or deceleration.

As the acceleration / deceleration amount setting device 190, a microcomputer 195 may be used as shown in FIG. That is, the setting tables shown in Tables 1 and 2 are stored in the memory of the microcomputer 195, and by inputting the amount of acceleration / deceleration corresponding to each oscillation circuit 110, each frequency divider is set in accordance with the amount of acceleration / deceleration. An H level signal may be input to the set terminal or the reset terminal 131 in accordance with the input timing of the logic slow / fast pulse (VCW). If such a microcomputer 195 is used, the amount of correction to be corrected can be adjusted even during operation. For example, a temperature sensor 196 may be provided so that the amount of correction can be adjusted according to the temperature during use. it can. With such a configuration, it is possible to correct a signal change of the oscillation circuit 110 due to a temperature change, and it is possible to obtain the logic accelerating / decelerating device 100 with extremely high accuracy.

Further, as the low delay signal input to the change timing synchronization circuit 161 of the signal delay absorption circuit 160, the output signal F16K of the frequency divider 131 of the first stage or the source signal may be used. When the pre-change signal generation circuit 165 of the above embodiment is used, the pre-change signal C changes one cycle before the 8 KHz signal with respect to the original timing, so that the 16 KHz signal is used as the low delay signal. When used, the change timing synchronization circuit 161 may be configured with two flip-flops, and when using the source signal (32 KHz), it may be configured with four flip-flops. When a low-delay signal of 16 KHz or 32 KHz is used, the pre-change signal C of the pre-change signal generation circuit 165 is set to change one cycle before each low-delay signal with respect to the original timing. It can also be composed of one flip-flop.

The present invention is not limited to an electronically controlled mechanical timepiece, but includes a battery type timepiece using a battery, a generator for generating electricity by rotating a rotor by a rotating weight, a piezoelectric element (piezo element), a solar cell, The present invention can be widely applied to a secondary battery that includes a secondary battery that stores power from a generator such as a thermoelectric generator and a motor that is operated by the secondary battery. However, an electronically controlled mechanical timepiece has a smaller generated voltage than a battery, a solar cell, a generator using a rotating weight, and the like. This is effective in that the hand operation can be controlled and the duration can be effectively extended.

The present invention can be applied not only to a case where the present invention is used for a timepiece such as a wristwatch or a table clock, but also to various devices which need to extract a highly accurate signal from the oscillation circuit 110. For example, the present invention can be applied to various devices that operate based on a frequency-divided signal, such as a device having a built-in clock function and a device having a timer function. Specifically, a portable blood pressure monitor, a mobile phone, a PHS, a pager, a pedometer, a calculator, a portable personal computer, an electronic organizer, a PDA
(Small information terminal, "Personal Digital Assistant"),
It can also be applied to portable radios, toys, music boxes, metronomes, electric razors, and the like.

Further, the mechanical energy source is not limited to the mainspring 1a, but may be a fluid such as rubber, a spring, a weight, or compressed air, and may be appropriately set according to the object to which the present invention is applied. Further, as a means for inputting mechanical energy to these mechanical energy sources, manual winding, rotating weight, potential energy, pressure change, wind power, wave power, hydraulic power, temperature difference, and the like may be used.

The energy transmission device for transmitting the mechanical energy from the mechanical energy source such as the mainspring 1a to the generator is not limited to the wheel train (gear) as in the above embodiment, but may be a friction wheel, a belt ( Timing belts, etc.), pulleys, chains and sprocket wheels, racks and pinions, cams, and the like may be used, and may be set as appropriate according to the type of target to which the present invention is applied.

The time display device is not limited to the hands 13, but may be a disk, a ring or an arc. Further, the logical regulation device of the present invention may be incorporated in a timepiece provided with a digital display type time display device using a liquid crystal panel or the like.

[0088]

As described above, according to the logic moderator of the present invention, by providing the signal delay absorbing circuit,
There is an effect that normal logical acceleration / deceleration processing can be performed even if the drive voltage decreases.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an electronically controlled mechanical timepiece according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a logical acceleration / deceleration device according to the embodiment of the present invention.

FIG. 3 is a circuit block diagram showing a circuit configuration of the logic moderator shown in FIG. 2;

FIG. 4 is a timing chart for explaining the operation of the logical acceleration / deceleration device of the embodiment.

FIG. 5 is a timing chart for explaining the operation of the logical acceleration / deceleration device of the embodiment.

FIG. 6 is a timing chart for explaining the operation of the logical acceleration / deceleration device of the embodiment.

FIG. 7 is a flowchart illustrating the operation of the logical acceleration / deceleration device according to the present embodiment.

FIG. 8 is a circuit block diagram showing a circuit configuration of a logical acceleration / deceleration device according to a modification of the present invention.

FIG. 9 is a circuit block diagram showing a circuit configuration of a logic moderator according to another modification of the present invention.

FIG. 10 is a circuit block diagram showing a circuit configuration of a conventional logic moderator according to the present invention.

FIG. 11 is a timing chart for explaining the operation of the conventional logic moderator shown in FIG.

FIG. 12 is a graph showing the operating voltage of the watch IC.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 logic slow-down device 110 oscillator circuit 110A crystal oscillator 130 frequency divider 131 frequency divider 140 timer 150 logic slow-fast timing pulse forming circuit 160 signal delay absorption circuit 161 change timing synchronization circuit 165 pre-change signal generating circuit 170 logic slow-fast pulse forming circuit 180 frequency divider circuit SET / RESET circuit 183, 184 wiring 185 select switch 190 speed setting device 191 pull-down resistor 193 wiring 195 microcomputer 196 temperature sensor 201a spring 207 speed-up wheel train 213 pointer 220 generator 220 power supply circuit 241 rectifier circuit 250 Rotation control device 253 Rotation detection circuit 255 Brake control circuit

Continued on the front page (72) Inventor Eisaku Shimizu 3-3-5 Yamato, Suwa-shi, Nagano F-term in Seiko Epson Corporation (reference) 2F002 AA07 AB06 AD00 AE01 CB12 GA04 2F082 AA01 DD08 HH00 JJ00

Claims (7)

[Claims] 1. A logical acceleration / deceleration device having acceleration / deceleration amount applying means for executing an acceleration / deceleration operation of a predetermined acceleration / deceleration amount by a start control signal with respect to a time reference signal generated based on a source vibration signal from an oscillating means, A logic regulation device comprising a signal delay absorption circuit for absorbing a delay of a logic regulation timing signal used for forming a control signal with respect to the source signal. 2. The logic deceleration device according to claim 1, wherein the deceleration amount providing means includes a plurality of frequency dividers for dividing a source signal from an oscillation means, and the frequency division circuit. A logic slow / fast timing signal forming circuit that forms the logic slow / fast timing signal by using a signal from the control unit; a start control signal forming circuit that forms the start control signal based on an output signal from the signal delay absorption circuit; A frequency setting device that sets a set state or a reset state of the frequency divider to allow adjustment of a predetermined acceleration / deceleration amount; and sets or resets a frequency divider circuit set by the acceleration / deceleration amount setting device by the start control signal. A frequency divider circuit control circuit for setting a state. 3. The logical acceleration / deceleration device according to claim 1, wherein the signal delay absorption circuit is configured such that when the logical acceleration / deceleration timing signal is in an active state, the signal delay absorption circuit generates the activation control signal more than a time when the activation control signal is originally generated. A pre-change signal generation circuit that generates a pre-change signal that changes before a predetermined time; and a start-up control signal that originally generates a change timing of an output signal based on a pre-change signal output from the pre-change signal generation circuit. And a change timing synchronizing circuit for adjusting to a point in time. 4. The logical acceleration / deceleration device according to claim 3, wherein the change timing synchronization circuit includes a data input terminal to which a pre-change signal from the pre-change signal generation circuit is input, and a delay with respect to the source oscillation signal. And a clock input terminal to which a low-delay signal having a small delay is input. 5. The logical acceleration / deceleration device according to claim 3, wherein the acceleration / deceleration amount providing means includes a frequency dividing circuit including a plurality of frequency dividers for dividing the source oscillation signal from the oscillating means. The low-delay signal is a source oscillation signal or a frequency-divided signal output from a first-stage or second-stage frequency divider of the frequency-dividing circuit. 6. A mechanical energy source, a generator driven by the mechanical energy source to generate induced power to supply electrical energy, and a rotation cycle of the generator driven by the electrical energy An electronically controlled mechanical timepiece comprising: a rotation control device that controls the rotation of the motor; and a time display device that is rotated together with the generator by the mechanical energy source and is speed-controlled by the rotation control device. An electronically controlled mechanical timepiece, comprising the logical acceleration / deceleration device according to claim 1. 7. A logical acceleration / deceleration method for executing a predetermined acceleration / deceleration operation by a start / stop signal with respect to a time reference signal generated based on a source oscillation signal from an oscillating means, wherein the start / stop control signal is formed. A delay of the logic acceleration / deceleration timing signal used for performing the above operation with respect to the source signal, and forming the activation control signal based on the signal in which the delay has been absorbed.