SU851757A1 - Pulse synchronizer - Google Patents

Description

-. .

The invention relates to a pulse technique and is intended for accurate synchronization of received pulsed signals relative to a clock frequency of a receiving device. A known pulse timing circuit comprising self-blocking logic circuits, delay elements and control triggers, based on the fact that the forward control has been memorized, based on the principle I is adopted. the fact of the arrival of the leading edge of the input pulse, the expectation of the beginning of the nearest sync pulse and its output at the output circuit nj. is

A disadvantage of the known synchronization scheme is that delay elements are used to provide the required time relationships between the input and the synchronization signals, which not only reduces the synchronization accuracy, but also limits the frequency tuning range and

duration of both input and sync signals.

The closest technical solution to the present invention is a pulse synchronization device containing two inverters, two elements that match, an RS flip-flop and element 2I-Sh1I, the output of which is connected to the output bus, and the first inputs of elements AND of element 2I-ШШ - with the outputs RS a trigger, the inputs of which are connected to the outputs of the coincidence elements, the first input of the first match element is connected to the clock pulse bus, with the second input of the first loop.

element AND of the element 2I-OR and the input of the second I

inverter, the output of which is connected

to the second input of the second element AND the element 2I-IPI and to the first input of the second element of the match 2.

The disadvantage of such a technical solution is the fact that the falling edge of the output pulse of the circuit is not synchronized at all, and therefore. At certain phase relationships between the interrogation signal and the synchronization signal, the duration of the output pulse is determined by the instant in time the interrogation signal is removed, which significantly reduces the accuracy. The purpose of the invention is to improve the synchronization accuracy, which consists in the reliable synchronization of both the leading and trailing edges of the output pulses. The goal is achieved by the fact that the pulse synchronizer, which contains two inverters, the input of the first of which is connected to the query bus, two coincidence elements, the RS flip-flop and the element 2I-OR, the output of which is connected to the output bus, and element 2I-IPI with the outputs of the RS-flip-flop, whose inputs are connected to the outputs of the matching elements, the first input of the first matching element is connected to the clock bus, with the second input of the first element And the 12I-SHS element and enter the second inverter whose output is connected To the second input of the second element AND element 2И-OR and to the first input of the second element of coincidence, the second RS-trigger and the third element of coincidence are entered, the first input of which is connected to the output of the element 2И-OR, the second input - with the output of the first inverter and with the input S of the second RS flip-flop 1 and the output with the input R of the second RS-flip-flop, the direct output of which is connected to the third inputs of the AND elements 2Y-LII, and the inverse output to the second inputs of the first and second elements of the match. The drawing shows a block diagram of the synchronizer. The synchronizer contains a request bus 1, which is connected to an inverter 2, the output of which is connected to the trigger point 3 and the input of the match element -4, the output of which, in turn, is connected to the R input of the RS flip-flop 3. The input clock is connected to the bus 5 clock pulses. inverter 6, First Input e:; match 7 and the second input of the First Element and Element 2I-OR 8; The OUTPUT of which is connected to the output gateway &. 9 .c iC the first input of the element 4 matches. The output of the inverter 6 is connected to. the first input of the element about PEEDEN} 10 and fco the second input of the second element AND the element 2И-Ш1И 8. The outputs of elements 7 and 0 coincidence are connected respectively to the R and S inputs of the trigger 11, the inputs of which are received from the first inputs of the elements AND element 2 II-OR 8. Pulse synchronizer works as follows. In the initial state, when there is still no request signal and, therefore, the output signal is also absent, high voltage levels are created at both inputs of element 4, and element 4 forcibly sets the RS flip-flop 3 to state O. Since the second The inputs of elements 7 and 10 are matches. . there is a high potential, and the first inputs alternately receive direct and inverse clock pulses, elements 7 and 10 alternately trigger, setting the RS-flip-flop 1I to the state O and 1 with the clock frequency. With the rising edge of the request pulses on bus 1, the inverter 2 sets the RS flip-flop 3 to state 1 and, thus, blocks further switching of elements 7 and 10 of the match, as well as the trigger I. Assume for definiteness that by the time of the arrival of the leading edge of the RS request pulse the trigger 11 is in the state O, i.e. At the first input of the coincidence element 7 at a given time, a high level of the clock pulse acts. The state of RS-flip-flop II corresponds to a low voltage level at the first input of the second element AND element 2И-OR 8, therefore this element AND in this case does not participate in the formation of the output signal. On the first . the input of the first element AND element 2И-OR 8 at the considered time also has a low level, however, after a period of time not exceeding half of the period of clock pulses. The change of level to high occurs, at the first inputs of element 2И-ШШ 8 a set of GGG appears, which leads to the formation of an output signal on bus 9, which will disappear after half a half clock frequency. If the request pulse ends earlier than the output pulse, this does not cause a change in the RS-Trigger 3 state, since the first match of element 4 is low

Claims (1)

The claims of the invention of which are the first 2I-OR soyevos A pulse synchronizer containing two inverters, the input of the first of 30 cells. Н 03 К 5/153. Of which is connected to the request bus, two matching elements, RS-trigger and 2-OR element, output is shared with the output bus, some elements AND elements are outputs of the RS-trigger, the inputs of which are connected to the inputs of the matching elements , the first input of the first coincidence element is connected to the clock bus, with the second input of the first element AND of the 2-OR element and the input of the second inverter, the output of which is connected to the second input of the second element AND of the 2I-OR element and to the first input of the second coincidence element, characterized in that, in order to increase I have synchronization accuracy, the second RS-trigger and the third coincidence element are introduced into it, the first input of which is connected to the output of the 2-OR element, the second input is with the output of the first inverter and with the input S of the second RS-trigger, and the output is with the input R of the second RS-flip-flop, the direct output of which is connected to the third inputs of the AND elements of the 2and-or-element, and the inverse output is connected to the second inputs. • the first and second elements of coincidence.