SU1075392A1 - Device for clock synchronizing and discriminating pulse burst - Google Patents

Abstract

A PULSE SYNCHRONIZATION DEVICE AND PULSE DEVELOPMENT OF A PULSE PACK, containing two triggers, two coincidence elements and an inverter whose output is connected to the C input of the first trigger, the forward output of which is connected to the S input of the second trigger and the first input of the first match element, the second input of which is connected with the first input of the second element of coincidence, it differs from the fact that, in order to expand the functionality, a trigger, an element of coincidence, an inverter and a pulse counter, the input of which is connected to the output of the second coincidence element, and an output coupled to the data input of the additional flip-flop, a second input and a second input of the coincidence element further inverter, whose output is connected to the input of the additional element nepBta4 coincidence, H-input of the pulse counter is connected to. the inverse output of the first trigger, the third input of the second match element and the n input of an additional trigger, the C input of which is connected to the second input of the first match element, the output of the inverter and the second input of the complementary matching element, 5 the third input of which is connected directly to the left additional trigger and R-input of the second trigger, the inverse output of which is connected to: H-input of the first trigger and the third input of the first match element, S and C-input of the second trigger connected to the input of the inverter.

Description

The invention relates to a pulse technique, in particular, to shapers, which temporarily assign an asynchronous signal to a clock frequency and, in addition, to form a series of pulses. A pulse shaper is known, containing two flip-flops and four NAND elements, two control buses and two clock-pulse buses. The device serves to form a single pulse or a series of clock pulses synchronous with the pulses of the master oscillator ij. A disadvantage of this device is that it does not have an output, at which a synchronized pulse is formed at the end of a series of pulses, as well as the dependence of the number of ictusks in a pack on the duration of the asynchronous control signal, i.e. in order to organize an automatic mode of operation, it is necessary to interrupt the control signal; and, which reduces the speed, the time signal of the control signal to the clock frequency is also required. In addition, for control, two sequences of clock pulses, which are shifted by half a contact with each other, are necessary. Closest to the invention is a clock synchronization device and a burst selection comprising two flip-flops, two coincidence elements and an inverter, the output of which is connected to the G input of the first flip-flop, whose direct output is connected to the S input of the second flip-flop and the first input of the first element match, the second input of which is connected to the primary of the second element of coincidence 2. Ned "x; tatka of a known device is that it does not have outputs on which pulses are synchronized to the clock frequency before it starts and after the formation of a series of pulses, as well as the dependence of the number of pulses in a packet on the duration of an asynchronous control signal, t . for the organization of the automatic mode, the interruption of the control signal is necessary, which reduces the speed. The aim of the invention is to expand the functionality of the device, which consists in the fact that before forming a burst of pulses and after forming a burst of pulses at separate outputs, the same pulses are synchronous to the clock frequency, and also eliminated. the dependence of the number of pulses in a burst on the duration of an asynchronous control signal. Exposure to automatic current (automatic mode without interruption of the control signal. The goal is achieved by the fact that the pulse synchronization device and the target burst containing two triggers, two matching elements and an inverter whose output is connected to the C input of the first trigger, the forward output of which is connected to the S input of the second trigger and the first input of the first match element, the second input of which is connected to the first input the house of the second coincidence element, an additional trigger, a coincidence element, an inverter and a pulse counter, whose counting input is connected to the output of the second coincidence element, and the output connected to the informational input of an additional trigger, the second input of the second coincidence element, and an additional inverter input, whose output connected to the first input of an additional element of coincidence, while the R input of the pulse counter is connected to the inverse output of the first trigger, the third input of the second matching element, and n-vh6dom additional trigger, the C-input of which is connected to the second input of the first matching element, the output of the inverter and the second input of the additional matching element, the third input of which is connected to the direct output of the additional trigger and the R-input of the second trigger, the inverse output of which is pinned to 1G - the input of the first trigger and the third input of the first match element, with the C input of the second trigger connected to the input of the inverter. Figure 1 shows a functional diagram of a clock synchronization device and a burst allocation; figure 2 - temporary diagrams bJ operation of the device. The device contains triggers 1-3, coincidence elements 4-6, inverters 7 and 8, a pulse counter 9, a control signal bus 10, a synchronization bus 11 and output buses 12-14. The control signal bus 10 is connected to the D input of the trigger 2, whose C input is connected to the synchronization bus 11 and the input of the inverter 7, the s input to the forward output of the trigger 1 and the first input of the matching element 4, R input to the forward output of trigger 3 and the first input of element 6 matches, and the inverse output to R input of trigger 1 and the second input of matching element 4, the output of inverter 7 is connected to the third input of matching element 4, first input of 5 matching element, second input of element b coincidence, C-inputs of flip-flops 1 and 3, inverse output of flip-flop 1 By connecting the second input of the coincidence element 5 to the F-inputs of the flip-flop 3 and the counter 9, D-input of flip-flop 3

connected to the third input of the element D in combination, the output of the pulse counter 9 and enter the inverter 8, the output of which is connected to the third input of the element 6 coincidence; the output of the coincidence element 4 is connected to the output bus 12, the output of the coincidence element 5 to the output bus 13 and the output of the pulse counter 9, and the output of the coincidence element b to the output bus 14.

The device works as follows.

In the initial state on the input bus 10, the signal level is low (Figure 2e). The clock pulses on the synchronization bus 11 (Fig. 20 at the output of the inverter 7 — pulses, inverse clocks, trigger 2 such pulses set to the zero state, a high level of the inverted output of trigger 2 sets the trigger 1 to the zero state and blocks the coincidence element 4 , a high level of the inverse output of the trigger 1 sets the trigger 3 and the counter 9 to the zero state and blocks the coincidence element 5, the high level from the output of the inverter 8 blocks the element 6 coincides, neither, on the output buses 12-14 - low levels (Fig.2g ,,, c).

The input asynchronous pulse (Fig. 2b) sets a high level at the B input of the trigger 2, and on the leading edge of the synchronization pulse, the trigger 2 is set to one, a low level from its inverse output (Fig. 2) allows the trigger 1 to open and opens the element 4 matches, at the output of which a high level appears (Fig. 2). On the leading edge of the pulse from the output of the inverter 7, the trigger | 1 is set to one state, a high level from the direct Bfc trigger trigger 1 blocks the trigger 2 in the unit state and the coincidence element 4 sets the low level on the pin 12. Low level from the inverse trigger output 1 permits the operation of counter 9, trigger 3 and open the coincidence element 5, allowing passage of the pulse pulses of the clock frequency through the inverter 7 and the coincidence element 5 to bus 13 and the counter 9 input (Fig. 2b). After the input of the counter 9 of the back edge of the t-pulse at the n-output of the counter 9, a high level appears, which is set at the D input of the trigger 3 and at the input of the inverter 8 and blocks the coincidence element 5, prohibiting further pulse propagation to the bus 13 and the input of the counter 9, a low level from the output of the inverter 8 opens the coincidence element b, allowing the clock frequency pulse to pass through the bus 14 through the inverter 7 and the coincidence element b (FIG. 2e), the positive difference at the output of the inverter 7 corresponding to the falling edge of the imp bca bus 14, sets the flip-flop 3 in edini5 chnoe state, a high level output from the forward flip-flop 3 (fig.2k) blocking member 6 and sets the coincidence flip-flop 2 in the null state, establishing a device to its original state, in the presence of

0 on the high level bus lOi, the cycle of operation of the device is repeated.

Thus, the sample, the proposed device can be used as generators of single pulses, generators of a series of pulses, and also allows two pulses, synchronous clock frequency and co-falling with it in duration: one before the start of a series of pulses | another, after the end of a series of pulses; When this happens, the device returns to its initial state, and when there is a control signal, the next cycle begins,. There are two possible modes of operation: standby and automatic. In standby peMfMe, the hand-held link of the asynchronous signal is controlled and controlled to the clock frequency, and in automatic mode the first single pulse of the next cycle follows a half-cycle of the clock frequency after the second single pulse of the previous cycle is formed, which co5 grows in auto | The time mode is one cycle for periods of clock frequency.

The proposed device possesses noise immunity on the control input: the signal duration sufficient to start must be such that the leading edge of the clock frequency must be in it, and after starting the device, regardless of the control signal, brings the cycle to an end.

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Claims (1)

A TACT SYNCHRONIZATION DEVICE AND ISOLATING A PULSE PULSE, containing two triggers, two coincidence elements, and an inverter whose output is connected to the C-input of the first trigger, the direct output of which is connected to the S-input of the second trigger and the first input of the first coincidence element, the second input of which is connected to the first input of the second coincidence element, distinguish it with the fact that, in order to expand the functionality, a trigger, a coincidence element, an inverter and a pulse counter are added to it, the counting input of which It is connected to the output of the second coincidence element, and the output is connected to the information input of the additional trigger, the second input of the second coincidence element and the input of the additional inverter, the output of which is connected to the first *! the input of the additional matching element, the R-input of the pulse counter is connected to. the inverse output of the first trigger, the third input of the second matching element and the R-input of the additional trigger, the C-input of which is connected to the second input of the first matching element, the output of the inverter and the second input of the additional matching element, S the third input of which is connected directly . by direct yield additional triggers and R- input of the second flip-flop, whose output is connected iiversny to | _(; B-input of the first flip-flop and a third "input of the first matching element 2 and the C-input of the second latch sub ~ key K input of inverter .