SU1092738A1 - Device for automatic discrimination of discrete communication channel errors - Google Patents

Abstract

A DEVICE FOR AUTOMATIC DETECTION OF DISCRETE COMMUNICATION CHANNEL ERROR containing the main and additional shift registers, dynamic trigger, decoder, inverter, first, second and third matching blocks, pulse counter and comparison unit, the first input of which is connected to the input of the main shift register with an adder feedback circuit, and a dynamic trigger output connected to the first shift input of the main shift register, characterized in that, in order to improve the accuracy of error detection by reducing time of detection and elimination of phase failure on the cycle, an additional pulse counter, a phase counter and a mode trigger are introduced, the output of the first matching block is connected to the write input of the additional shift register and the second matching block output, the second input of the comparison unit is connected to the first bit output shift register, the output of which is connected to the first input of the second coincidence unit, the second input of which is connected to the output of the inverter, the input of which is connected to the first input of the first block with flow, with the reset input of the additional pulse counter, with the reset input of the phase counter, with the reset input of the mode trigger, with the first i shift input of the additional shift register, with the second input the shift of the main shift register and with the input g of the dynamic trigger setting, you (L connected to the second input, the house of shift of the additional register from the shift and with the counting input of the additional pulse counter, the output of which is connected to the third input of the shift of the main shift register, with the reset input of the pulse counter, s xsadom of setting the mode trigger and with the counting input of the phase counter, the output of which is connected to the reset input of the dynamic trigger, with the output of the trigger mode and with the first input of the third matching unit, the second input of which is connected to the counting input of the pulse counter and the output of the Comparison, and the outputs of the main shift register are connected to the corresponding inputs of the decoder, the output of which is connected to the write input of the main shift register.

Description

The invention relates to electrical communication and can be used in instrumentation communication equipment and data transmission equipment.

A device for automatically detecting discrete communication errors is known, comprising a main shift register and an additional shift register, the outputs of which are connected to the inputs of the decoder, the inverter, a matching unit, a pulse counter and a comparison unit, the first input of which is connected to the input of the recording of the main shift register with the adder feedback circuits G J 3

The disadvantage of this device is the low accuracy of error detection due to the long-term detection and elimination of phase failure in the cycle.

It is also known a device for automatically detecting errors of a discrete communication channel, comprising a primary and secondary shift registers, an inverter, a junction block, a decoder, a pulse counter and a comparison unit, the first input of which is connected to the input of the main shift register with an adder in the circuit. feedback C2 3. A disadvantage of this device is also the low accuracy of error detection due to the implementation of frame synchronization at a valid interval. The closest to the invention in its technical essence is a device for automatically detecting errors of a discrete communication channel, containing the main and additional shift registers, a dynamic trigger, a descrambler, an inverter, a first, second and third matching blocks, a pulse counter and a comparison unit, the first input of which is connected to the input of the record of the main shift register with the adder in the feedback circuit, and the output of the dynamic trigger is connected to the first input of the shift of the main shift register G 3 3. However, this device does not provide high reliability of detecting errors and sufficiently fast elimination of phase failure in a cycle in low quality channels (with an average probability of an error per symbol 10). In channels of this quality, the probability of occurrence of 20-60 characters is small without error and, therefore, a known device that synchronizes over cycles at a valid interval will give

unreliable data. In addition, the known device does not quantify the magnitude of the phase failure in a cycle, i.e. how many clock cycles the received sequence is relative to the transmitted one.

The purpose of the invention is to improve the accuracy of error detection by reducing the time for automatic detection

10 and eliminating a phase failure on a cycle.

The goal is achieved by the fact that the device for automatic detection of errors of a discrete communication channel, containing the main and additional

15 shift registers, dynamic trigger, decoder, inverter, first, second and third matching blocks, pulse counter and comparison unit, the first input of which is connected to the recording input of the main shift register with an adder in the feedback circuit, and the output of the dynamic trigger are connected with the first shift input of the main register-. a shift, an additional 25 pulse counter, a phase counter and a mode trigger are introduced, the output of the first coincidence block is connected to the write input of the additional shift register and the output of the second block is the same, the second input of the comparison block is co. single with the output of the first bit of the additional shift register, the output of which is connected to the first input of the second matching unit, the second input 35 of which is connected to the output of the inverter, whose input is connected to the first input of the first matching unit, to the reset input of the additional pulse counter, to the reset input of the phase counter , with the reset input of the trigger mode. with the first shift input of the additional shift register, with the second shift input of the main shift register and the setup input of the dynamic trigger, the output of which is connected to the second shift input of the additional shift register and with the counting input of the additional Pulse counter, the output of which is connected to the third shift input of the main shift register , with the reset input of the pulse counter, with the installation input of the mode trigger and the counting input of the phase counter, the output of which is connected to the reset input of the dynamic trigger, from the output Trigger Mode uc house the first input of the third block matching between the second input of which is connected to the counting input of pulse counter and a yield 6noka comparison, a main outputs Giustra shear coupled to corresponding inputs of the decoder, the output of which is connected to the input of recording the main shift register. The principle of operation of the device is based on the correlation properties of hapses used as test patterns for random: sequences in studies of discrete communication channels. When receiving each successive symbol, the device compares the sequence of the next N symbols received from the channel (where, N is the length of the period, the t-sequence) with the T phases of the reference sequence, t, e, is calculated the correlation function between the incoming sequence and N phases The correct phase is determined by the reference sequence and the maximum of this function. Thus, a phase failure can be eliminated during the arrival of one character in a very poor quality channel. The drawing shows the structural electrical circuit of the device. The device for automatic detection of discrete communication channel errors contains the first and second blocks 1 and 2 matches, additional shift register 3, comparison block 4, inverter 5, additional pulse counter 6, phase counter 7, mode trigger 8, main shift register 9 , adder 10, dynamic trigger 11, pulse counter 12, the third block 13 of the match and the decoder 14. I The device works as follows. The binary sequence from the discrete communication channel through the first block 1 of coincidence arrives at the input of the additional shift register 3, the second input of the first block 1 coincides with the clock sequence from the discrete communication channel, which also performs the initial setting of the phasing scheme, namely the shift of the main and additional registers 9 and 3 of the shift, the start of the dynamic trigger 1 1, the reset to the additional counter 6 pulses and the counter 7 of the phase, the reset trigger 8 of the mode. After the end of the clock pulse, the additional register 3 of the shift is closed into the ring through the second block 2 of coincidence, the second input of which receives the clock sequence through the inverter 5,. The signal from the lower bits of the main and additional registers 9 and 3 of the shift is fed to the inputs of the 4 comparison unit, the output of which detected erroneous characters are applied to the input of the counter-12 pulses, as well as to the output from the device for recording through the third block 13 matches, the second input of which receives a signal from the output of the trigger 8 of the mode, signifying the completion of the phasing process at a given clock cycle. To improve the accuracy of detecting errors of the discrete communication channel, it is necessary to exclude the state of the main shift register 9, When ;; cat, torus all its bits ravshl zero, since in this case does not generate the shift register sequence. Therefore, the outputs of the bits of the main shift register 9 are connected to the inputs of the decoder 14, which reacts to the denied state and sets the first bit of the main shift register 9 to one. The automatic calculation of the phase C on the cycle between the binary sequence coming from the channel and the sequence generated by the axis of the shift register 9, and the elimination of this failure is carried out in a c / ie in a manner. The pulse sequence from the output of dynamic trigger II is fed to the shift inputs of the main and auxiliary registers 9 and 3 of the shift, and is also counted by: a pulsed counter 6 pulses of capacity N. The number of discrepancies from the output of the comparison unit 4 is counted by a pulse counter 12, having the threshold element output The signal at the output of the pulse counter 12 appears when the number of mismatches is less than a certain threshold M, t, e, the sequences are phased. After the end of the N-shift. The signal from the output of the additional pulse counter 6 records information from the output of the pulse counter 12 to the mode trigger 8, resets the pulse counter 12 and enters the input of the phase counter 7. In the absence of phase failure, a signal appears at the cycle a mode trigger 8, signifying the completion of the phasing process at a given clock cycle, which, moreover, is supplied to resetting the oscillations of a dynamic three ger 11. In the phase counter 7, a unit is recorded at the same time, meaning that synchronization with the cycle on this clock cycle is not is happening. If the binary sequences on this clock are not phased, then the entire sequence of operations is repeated, taking into account that the base sequence of the main shift register 9 is shifted in phase by one by the signal. From the output of the additional counter of 6 pulses until the sequences will not be phased, while the phase counter 7 in the phase 7 contains an increased by one value of the phase loops on the cycle. If in none of the N phases of the reference sequence the number of errors is less than the threshold M, then the oscillation of the dynamic trigger 11 is reset by a signal from the output of the phase counter 7, whose capacitance is N, the phase of the reference sequence remains the same as in the previous cycle. The technical and economic efficiency of the device consists in improving the accuracy of detecting errors of a discrete communication channel of poor quality (average error probability per character (1-3) -... Moreover, since the monitoring of the fidelity of the frame sync tions vedets on receiving each clock cycle, the elimination SRB synchronization cycles is accomplished during one clock cycle, i.e., in the shortest possible time. The device also permits further determine the amount of divergence phases failover frame synchronization.

Claims (1)

DEVICE FOR AUTOMATICALLY IDENTIFYING ERRORS OF A DISCRETE COMMUNICATION CHANNEL, containing primary and secondary shift registers, a dynamic trigger, a decoder, an inverter, first, second and third coincidence blocks, a pulse counter and a comparison unit, the first input of which is connected to the input of the main shift register record with the adder feedback circuit, and the output of the dynamic trigger is connected to the first shift input of the main shift register, <characterized in that, in order to increase the accuracy of error detection by reducing the time and detecting and eliminating a phase failure in a cycle, an additional pulse counter, a phase counter and a mode trigger are introduced, while the output of the first coincidence unit is connected to the recording input of the additional shift register and the output of the second coincidence unit, the second input of the comparison unit is connected to the output of the first discharge of an additional • shift register whose output (connected to the first input of the second coincidence unit, the second input of which is connected to the output of the inverter, the input of which is connected to the first input of the first coincidence unit, with by resetting the additional pulse counter, with the input of the phase counter reset, with the input ^{1 of the} mode trigger reset house, with the first ί shift input of the additional shift register, with the second shift4 input of the main shift register and with the installation of the dynamic trigger setting, the output of which is connected to the second shift input additional shift register and with the counting input of the additional pulse counter, the output of which is connected to the third input 5 t of the shift of the main shift register, with the reset pulse counter input, with the trigger setup input The mode mode and with the counter phase input, whose output is connected to the reset input of the dynamic trigger, with the mode trigger output and with the first input of the third coincidence unit, the second input of which is connected to the counter pulse input and the output of the comparison unit and the outputs of the main shift register are connected to the corresponding inputs of the decoder — j of the torus, the output of which is connected to the recording input of the main shift register.