DK161234B - DEVICES FOR TRANSMISSION OF DIGITAL INFORMATION SIGNALS - Google Patents

Abstract

1. System for the transmission and reception of digital information signals, especially for the digital transmission of sound by way of satellites, in which the data sequences are arranged following one another in time a block and in which in the receiver the block is divided in two timewise parallel part blocks (A, B) representing the data sequences, characterized in that each part block (A, B) exhibits a synchronisation word of an equal or equivalent type of equal length, that for the time recognition and if necessary for the compensation of the phase position of the part blocks (A, B) a correlator (3, 5, 7; 4, 6, 8; 3, 7, 14, 15, 44, 47-52) is used for each part block, that for the synchronisation code words are used which exhibit an unequivocal maximum of their autocorrelation function for the instant T = O, and that the auto correlation function for all instants T Not = O is effectively minimal.

Description

DK 161234 B

The invention relates to a facility for digital information signal transmission, in particular for digital transmission over satellites, as defined in the preamble of claim 1.

5 In a bit data transfer, the code blocks, namely frames and possibly subframes, are periodically repeated. In order to properly decode the data blocks, it is necessary to determine the temporal location of the frame. By using self-synchronizing codes, the bandwidth of the transmission is increased by increased redundancy request. A so-called comma code, which is a block code that is embedded between synchronization patterns, avoids a noticeable increase in bandwidth. In particular, with a four-phase CPSK modulation (Co-15 herent Phase Shift Keying Modulation), data generation is ensured using a comma code based on the frame structure.

Each transmission block in the digital signal contains a preset password, synchronization word, which serves for synchronization detection. Then there is usually a sequence of data passwords which also contain control information.

On the transmission line to be considered, time errors and amplitude errors may occur. At the rate of regeneration, time errors cause so-called bit slips.

Amplitude errors, i.e. bit inversions, falsifying data and syncing words. Using a four-phase CPSK modulation, it is necessary to compensate the ambiguity of the phase modulation in data generation. From the literature, sync words (Barker, Maury) are known, where a small number of bit errors in a sync word do not affect the uniqueness of the sync word detection.

DE-A 1 30 13 554 discloses a digital transmission system in which synchronization words in a single 35 data stream are serially transmitted and processed. Two comparators that do not work at the same time are used to examine the data flow for different synchronizations

DK 161234B

2 words. With this technique, elimination of phase ambiguity is not possible.

The invention therefore aims to improve a digital information signal transmission system for detecting the temporal location of the data stream and to compensate for the influence of time errors, amplitude errors and phase ambiguities.

The task is solved with the invention according to claim 1. Further embodiments of the invention are described in the subclaims.

When using the system according to the invention, the temporal location of the frame is ascertained with sufficient certainty. The length of the synchronization word is relatively short relative to the frame length and the associated redundancy is minimal. The synchronization words are chosen so that a synchronization outcome occurs much less frequently than uncorrected errors in the information.

For the receiving side's detection of the synchronization words, the words must be considered in a special time location in correlators. The synchronization words according to the invention contain in the undistorted state of the autocorrelation function, i.e. for the time T = 0, a pronounced maximum. For all times T # 0, the autocorrelation function is minimally in size.

A CPSK modulation has a phase ambiguity. This may cause the sync word to arrive in inverted state at the receiver. Therefore, the synchronization words exhibit at all times T ^ O a very small difference between autocorrelation function and inverted autocorrelation function, so that the synchronization words can be detected safely also in the inverted state.

DK 161234B

3 The ambiguity of the CPSK demodulation can be compensated by utilizing the correlation function formed in the receiver between the stored and received sync words. The temporal location of the frame start is determined by the result of the value determined in the correlator and a post-coupled logic threshold coupling insofar as the control signals derived from the two correlators are fed to a logic circuit which is interrogated in a defined time window.

For correction of time errors that can lead to a 10 bit slip, it is suggested to check the cross correlation function in a slightly wider time window. Based on the location of the maximum cross-correlation function in this time window, the occurrence and size of a bit clip can be immediately concluded and corrected for the next frame. For this, the cross-correlation function for time T = 0 must be greater than the cross-correlation function for time T ^ Q. However, this is only possible until a maximum number of bit errors in the sync word. The maximum allowable 20 number of bit errors, the greater the longer the sync word is selected. A favorable compromise was derived between the two claims for low redundancy and high residual error probability.

With the synchronization words, at a length 25 of the 16 bit synchronization word, up to 3 arbitrary bit errors in a synchronization word can be allowed without losing the uniqueness of the synchronization word detection. If the window width for checking the synchronous word is more than 1 bit, it must be taken into account that the synchronous word 30 may be falsified due to bit errors caused by the defective channel and by neighbor data.

With the synchronization words, at a window width of five beats with a logical threshold coupling, bit slips of up to ± 2 beats can be detected and the 3 ^ temporal shift can be eliminated. In order to fulfill the criterion that the outcome of the synchronization must occur significantly less than the maximum

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If a permissible residual error probability of non-correctable false information is given, it is suggested by dividing the main frame into two subframes (bit planes A and B) for synchronization in both subframes to use a similar or equivalent pattern of the same length. With a correlator for each of the subframes A and B, both synchronous words can be controlled simultaneously, from which the temporal location of the frame is determined and the ambiguity of the phase modulation is eliminated. As a result of using this system for frame synchronization, synchronization errors occur only when both synchronization words are disturbed by every four bit errors.

The invention is described in more detail below on the basis of an exemplary embodiment.

15 In the drawing:

FIG. 1 is a block diagram utilizing the synchronization words in subframes A and B; FIG. 2 is a block diagram for determining the cross-correlation function; FIG. 3 shows a fork coupling; FIG. 4 and a table, FIG. 5 shows a coupling for determining the location of the synchronization word; and FIG. 6 a process control.

FIG. 1 shows a block diagram for finding the synchronization words. The signal arriving at terminal 1 is supplied with a 4-phase demodulator 2 (CSPK). The data stream is divided into two bit planes A and B. Since the demodulation in the CPSK demodulator 2 is ambiguous, the signals A, B may appear inverted or non-inverted, ie. there are two options for each bit plan. The data in each bit plane is output to shift registers 3 and 4, respectively. By comparing the data entered in shift register 3, 4 with the synchronous word permanently coupled by a coupling 44 (Fig. 2), the cross-correlation function is formed in steps 5 and 6, respectively. Every 5

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of steps 5 and 6 are storage components which are divided into two parts. By adding the contents of the called addresses to the storage in the addition steps 7 and 8, respectively, the value of the cross-correlation function can be determined 5. A subsequent logical threshold coupling 9 and 10 respectively, on the basis of the added cross-correlation value, assess whether the sync word or its inversion or no sync word has been received. In step 11, the temporal location of the synchronization word is determined and the internal frame rate is optionally re-regulated. It can also be ascertained whether the sub-data streams A and B have been received in inverted, non-inverted and / or exchanged states. Optionally, by means of the fork coupling 12, the partial data streams 15 are corrected.

FIG. 2 shows a diagram for determining the cross-correlation function. From the terminal 13, the data stream reaches serially into the shift register 3. Above the parallel outputs of the shift register 3 there is a bit-20 sequence of 16 bits. Every 8 bits of the data words located above the parallel outputs of the switch register 3 are over exclusive OR gates 47-49 and 50-52 respectively compared to the corresponding sub-code word of the synchronization word. The outputs of the exclusive OR gates 25 are routed to a prom (PROM = programmable read only memory) 14 respectively 15. The above data outputs on the 8 or the exclusive OR gates 47-49 and 50-52 respectively indicate an address in the prom link circuits 14 or 15. The contents of the named storage locations in the promo circuits 14 and 15 are output to an addition stage 7. Depending on the password, which is on the outputs of the switch register 3, specific addresses are called in the promo circuits 14 and 15 which call for a storage content between -4 and +4 binary coded which corresponds to the present number of matches. The addition in the addition step 7 gives the value of the cross-correlation function (-8 to \ 6

DK 161234 B

+8). The two bits with the highest value in the stock contents of the prom coupling circuits 14 and 15 are output to an exclusive OR gate 16. The output of the exclusive OR gate 16 and the space with the highest 5 value on the output link 71 s output leads to a further exclusive-OR gate 17, the output of which is the bit of the highest value in the cross-correlation value appearing at the output of the addition 7 in 2s complement. The output of the addition link 7 together with the output of the exclusive OR gate 17 constitutes the definite value of the cross-correlation function produced in 2's complement.

The output of the exclusive OR gate 17 is the bit of the highest value and thus constitutes the sign of the cross-correlation function.

With the values of the addition link 7's output and the exclusive OR gate 17's output, an additional promo circuit 18 is activated.

If the 20 address code words above the promo circuit 18 with respect to their value exceed a predetermined threshold, the corresponding storage locations are characterized by logical "1". A named storage contents logic "1" delivered above the terminal 19 indicates the detection of a synchronization word, indicating in the state of the terminal 22 whether an inverted or non-inverted state exists.

FIG. 3 shows a fork coupling controlled by signals E and F over terminals 22 and 30 23.

The signals E and F come from the correlators for bit planes A and B and corresponding to the bits with the highest value in the correlator output signal for A and B.

7

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The coupling in FIG. 3 is constructed according to the following structure: C = (E.F + É.F). (A.É + AE) + (E.F + FE) · (B.F + BF) D = (E.F + É.F) · (B.F + BF) + (E.F + É. F) · (A.É + AE)

The output signals C and D in the embodiment of FIG. Fork coupling terminals 24 and 25 appear at an input signal A and B above terminals 20 and 21 according to the control information over terminals 22 and 23.

Using this coupling, two data streams can either be exchanged or / and inverted (see Fig. 4).

FIG. 5 shows a coupling for detecting the location of the synchronization pattern in the frame. The terminals 19 and 27 are fed to the signals from the storage locations in a prom coupling circuit 18 as shown in FIG. 2. There is a shift register 28 and 29 for each part-15 frame. The switch registers 28 and 29 each contain five bit cells to whose center values are connected to an AND gate 30. Furthermore, there are strobe inputs 31 and 32. The parallel outputs on the switch register 28 and 29 lead to a 1024 x 4 promc link circuit 33 The contents of the named storage locations in the prom switching circuit 33 are fed to an addition link 34 which is also supplied with counter positions from a pre-programmable frame counter 26, 36. In the example shown, the counter in each case counts up to an address 320. Once the counter has reached its end address, its charging input 37 is supplied with a pulse and the counter is reset to the pre-programmable output state.

For the first search for the frame rate, the restart input 39 is supplied with a signal which resets the counter 36. At the same time, the strobe inputs 31 and 32 on the shift registers 28 and 29. are invoked over the OR gate 40, since the outputs of the shift registers 28 and 29 lead to the promo circuit 33 , invoked in

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8 in each case a specific address in the prom link circuit 33. The outputs on the logical correlator threshold for bit planes A and B are connected via terminals 19 and 27 to the serial inputs on switch registers 5 19 and 27.

Above the terminal 38 is the location of the time window, which has been recovered from the process control. It is delivered over the STROBE port 40 to the strobe inputs 31 and 32.

TO The information which, after 5 in the time window, incremental rate steps are entered in the switch registers 28 and 29, is then utilized by means of the promo circuit content 33. The content of the storage at the called address gives the addition link 34 information 15 about how far the current rate step is. removed from the frame rate. At the desired location of the synchronization rate, the clock is in the middle storage cells of the switch registers 28 and 29. Above the AND gate 30 connected there is an impulse to the terminal 41. Over a connected logic utilization circuit shown in FIG. 6, an impulse is delivered across the terminal 39 to the charging input 37. The counter 36 thus begins to count again. If the desired location is not reached, e.g. as a result of a bit slip, the counter count of the count 36 36 is changed over another called address in the prom link circuit 33. Thus, the rate synchronization of the frame is shifted correctly.

FIG. 6 shows a logical utilization link for controlling the course of the search and hold process. Terminals 30 22 and 23 are supplied with the location information of the synchronous word from the two subframes A, B. As soon as the synchronous word is in the correct temporal location, the input terminal 41 from the AND gate 30 receives a pulse. The search mode is triggered by a state switch to logic 1 across terminal 38 leading to OR port 40. An impulse across terminal 39 passes over a OR

Claims (8)

15 PATENT REQUIREMENTS 1. Devices for transmitting and receiving digital information signals, in particular for digital audio transmission over satellites, where the data sequences are located temporally in succession in a frame and wherein the frame of the receiver is divided into temporally parallel subframes (A, B) representing The data sequences, characterized in that each subframe has a synchronization word of the same or equivalent type of the same length, that for the temporal detection of 25 and possibly. to compensate for the phase position of the subframes (A, B), one correlator (3.5,7; 4.6.8; 3.7,14,15,44,47-52) is used. subframe (A, B) that for synchronization, passwords that have a unique maximum of their autocorrelation function for the time point T = 0 are used and that the autocorrelation function for all time points T0 is minimal. DK 161234 B System according to claim 1, characterized by using one of the following synchronization words / their inversion, mirroring (read from behind) or inverted mirroring, O being logical O and 1 being logical 1: 5 1. 0110100001110111 2. 0101101110111000 3. 0100100010001111 4. 0100010010111100 System according to claim 1, characterized in that a coupling (Fig. 5) exists for detecting the temporal location of the synchronization word and for correcting the temporal location of the frame. System according to claim 1, characterized in that there is a switch for switching (Fig. 3) of the arriving data streams (A and B), which coupling is controlled by a synchronization word detection switch. System according to claim 1, characterized in that the presence of the synchronization word is checked twice for the first search or retransmission of the synchronization state, respectively. System according to claim 1, characterized in that there are two operating states in which the synchronization pattern presence is checked twice in a first operating state and, in the event that the synchronization pattern is detected, coupled to the second operating state in which the phase location of the data sequence is checked. of ± 2 bytes from the normal state, and when deviating from the normal state, a temporal correction occurs immediately in the next frame. System according to claim 1, characterized in that two storage components (14, 15) are used for determining the synchronization word, the outputs of which are provided over an addition coupling (7), the value of the cross-correlation between the agreed and received synchronization word. DK 161234 B Coupling according to claim 1, characterized in that a logical threshold coupling is provided containing a storage component (18) in which an address below each of which cross-value values are stored, representative of the states: sync words exists, inverted sync words are present and no sync words are present.