DE3500363A1 - Arrangement for the synchronisation of a digital data receiver - Google Patents

Abstract

Arrangement for the synchronisation of a digital data receiver to the bit clock and frame clock of a received data stream by correlation of a received frame alignment signal with a reference frame alignment signal stored in the data receiver. The correlation is performed in a digital correlator in time steps of 1/N bit lengths, N = an integer. When a frame alignment signal is detected, the correlator emits a setting pulse, from which the bit clock and frame clock are simultaneously derived.

Description

Arrangement for the synchronization of a digital data

receiver The invention relates to an arrangement according to the preamble of claim 1.

The basic principle of frame synchronization by correlating the received Data with a known frame sync word is z. B. by J. Eldon in Correlation ... a Powerful Technique for Digital Signal Processing ", LSI Publication TP17B-4/81, TRW LSI Products. When transmitting serial data, e.g. B. of a PCM multiplex system via radio, is the fast resynchronization after data failure especially important as well as the ability to act well (by transferring) easily to be able to correctly synchronize disturbed synchronous words.

The object of the invention is to provide an arrangement of the type mentioned at the beginning Type of specifying with which a secure, fast, and simultaneous synchronization at bit rate and frame rate is possible. The invention is characterized in claim 1. Claim 6 describes an inventive development of the arrangement. The others Claims contain advantageous embodiments of the invention.

The invention is explained in more detail below.

Assume that data is transmitted over a channel in frames which follow each other periodically and each consist of a synchronous word of k bits, followed by i-1 words of k bits each, i.e. consisting of i.k bits.

The synchronizer according to the invention in the data receiver compares now continuously the received digital data with the known reference sync word in time steps of 1 / N bit lengths, N = whole number, through correlation. To do this, the received signal is clocked into a correlator with N times the bit clock. That The synchronous word received with a length of k bits is expanded into a word with a length of k N chips and compared with the reference sync word, which has also been expanded to a k-N chip length; the temporal resolution of the comparison is therefore 1 / N bit length.

The received sync word is considered recognized if it is in MS k-N chip matches the reference sync word. The threshold M of the correlation value is adjustable; it can be up to N-1 chip below the maximum correlation value k-N lie with completely undisturbed reception. This can also be done on slightly disturbed sync words correctly synchronized.

The correlator emits a set pulse when the sync word is recognized from which the bit rate and frame rate can be derived simultaneously in a simple manner can. This is preferably done by means of a clock divider chain, which through the set pulse can be reset. The factor N is advantageously the same chosen to a power of 2L, L = integer. If the threshold M becomes smaller than k * N chips If the reception is completely undisturbed, the frame rate is faster than the incoming (Iell Data stream by (k-N-M) chips before (without taking into account gate delay times, etc.). This difference can be easily achieved by a fixed delay element (delay) can be compensated, so that correct decoding (interrogation) within one bit length is possible.

When the synchronous word is first recognized, the bit and frame clocks are now set synchronized by resetting the dividing chain; the reset is preferred for the following words until shortly before the start of the next expected synchronous word locked, so z. B. for i-1.5 data words.

This prevents sporadic data contained in the data random sync words lead to incorrect synchronization; so no bit sequences are required excluded as inadmissible in the data (such as the possible

scrambled A S signal in certain PCM systems). Wrong initial syncs synchronous words in the data are corrected in the synchronizer according to the invention by the next correct synchronous words automatically. However, it is advisable to as synchronicity a word with good autocorrelation properties and - if possible - to use low cross-correlation with the transmitted data to determine the probability to keep it low for an incorrect initial synchronization.

An embodiment of the invention is shown in the figure. It is a synchronizer for a PCM frame with 8 kHz frame clock, Consisting of three data words (PCM time slots) and one synchronous word of each 8 bit length; the bit clock is consequently 256 kHz. With correspondingly higher clock rates can frame z. B. use 32 time slots. In the exemplary embodiment is N = 23 = 8.

A mother clock generator generates in a transistor circuit with quartz a sinusoidal signal with a frequency of 2.048 MHz. The sine signal is with a Another transistor amplified to TTL level and buffered with two TTL gates. With this chip clock generated by the mother clock generator, the correlator and the dividing chain clocked.

A first binary counter is reset when the operating voltage is switched on and released after approx. 20 ms.

A loading logic switches a subsequent first shift register in the first time cycle on load and the reference sync word is in parallel in the shift register invited. In the second cycle the shift register is switched to serial shift and clocked the sync word into the correlator. The correlator itself is using the 8-fold clock rate (mother clock) clocked, so that the synchronous word length in the correlator 64 bits, this results in a maximum correlation accuracy for one bit of the synchronous word of 1/8 bit (depending on the set threshold value). The last bit of the 1.

Binary counter on high, then a NOR gate at the input of the 1. Binary counter its own clock and that of the correlator (CLKB).

The correlator is functional after the reference sync word has been loaded. The received NRZ data stream is at its input AIN. It is with the reference sync word compared. The correlation threshold M (binary) can be set at the threshold register value switch can be set. If the synchronous word and the data word correlate, a setting pulse is generated on the TFLG (Trigger) issued.

The divider chain consists of a second binary counter and a row D flip flops. Both are clocked with the mother cycle (chip cycle). At the data inputs the level of the corresponding counter outputs of the second binary counter lie on the flip-flops at. This is reset from the correlator's set pulse, such as RcHatlog-ik. Noboll bit clock and frame clock are further auxiliary clocks in the exemplary embodiment derived from the divider chain, in particular clocks for the time slots (data words). The blocking signal for the setting pulse is also derived from this component (decoder) (or an enable signal for the reset logic at the beginning of the fourth data word / time slot).

With every set pulse, i.e. with every correctly recognized sync word, the divider chain is reset and, as a result, the bit clock and frame clock are re-synchronized. Shifts in synchronism between synchronous pulse and data stream due to Drift of the master clock generator or changes in runtime in the transmission channel so regularly balanced. Phase fluctuations caused by setting the threshold M depend on the correlation value and by recognizing slightly disturbed sync words do not affect the decoding of the data. Will not Synchronous word recognized, not even over longer periods, the divider chain runs, and thus bit rate and frame rate, freely continuing with the mother rate.

- blank page -

Claims (7)

Claims arrangement for the synchronization of a digital data receiver on bit clock and frame clock of a received data stream by correlating a received synchronous word with a reference synchronous word stored in the data receiver, characterized in that the correlation in a digital correlator in time steps of 1 / N bit lengths, N = whole number, and that when the synchronous word is recognized, the Correlator emits a set pulse from which bit clock and frame clock simultaneously be derived. 2. Arrangement according to claim i, characterized in that the factor N is selected to be equal to a power of 2L L = integer. 3. Arrangement according to claims 1 and 2, characterized in that Bit rate and frame rate are generated by a divider chain, which is N-fold of the bit clock is clocked and can be reset by the set pulse. 4. Arrangement according to claims 1 to 3, characterized in that a mother clock generator generates a clock with N times the bit clock and that the correlator and the divider chain are clocked with this clock. 5. Arrangement according to one of the preceding claims, characterized in that that the correlation value of the correlator is adjustable. 6. Arrangement according to one of the preceding claims with in the data stream repetitive sync word, characterized in that the set pulse only is used for synchronization when the sync word is in the expected place in the frame occurs. 7. Arrangement according to claim 6, characterized in that the setting pulse is blocked for a specified time after recognition of a synchro word.