DE4316494C1 - Clock synchronisation for received digital signal - using frequency divider reset by received digital signal, providing clock signal for sampling stage - Google Patents

Abstract

A resettable frequency divider (2) is operated at a frequency which is a multiple of the received digital signal (DS); its resetting input (4) being supplied with a resetting pulse (RS) derived from the latter via a flank detector (5, 6). The frequency divider provides a clock signal for a sampling stage (8) receiving the digital signal (DS), at its divider output (3), at half the digital information step length. Pref., the flank detector uses an Exclusive-OR gate, or an Exclusive NOR gate with a timing element (6) across its inputs. ADVANTAGE - Provides synchronisation at high data rate with reduced circuit complexity.

Description

The invention relates to digital clock synchronization according to the preamble of claim 1.

With digital data transmission it is necessary that in phase and frequency from the received digital signal deviating clock signal of the receiving device to synchronize sieren. Different methods are known for this.

In "AEÜ", Nov. 1968, Issue 11, page 509-513, several suggestions for clock synchronization are provided. The aim of every synchronization is to scan the received data steps (bits) in the middle if possible. Figure 1 of this literature point shows a clock synchronization in which the clock edges of the digital signal are compared with the receiver clock and, depending on the deviation, a phase correction is carried out by adjusting a division ratio. In addition, an improved, more stable variant is specified.

There is also a restart synchronizer in this reference described the method used for start-stop operation becomes. A start step of a data word hits a clock generator, which delivers sampling clocks until the stop pulse, with where the data steps are scanned.

From European patent specification 0 275 406 B1 a Ver drive known for the recovery of the clock, at - control by a phase discriminator - by several against each other the other phase-shifted receiver clock the appropriate one is chosen.

With digital signals with a low data rate, there is also numerous syn or counting methods using integration  chronizations, however, because of their high wall and circuit run times for many applications are unsuitable.

The object of the invention is suitable for high data rates Nete synchronizer with little circuitry specify.

This object is achieved by the specified in claim 1 Synchronizer solved.

The main advantage of the synchronizer according to the invention In addition to the low amount of circuitry required, the device is in the reliable way of working. Metastable states occur not on.

This is also particularly advantageous for many applications abrupt synchronization with the first edge of the Digi valley signal.

In a circuit variant, it is advantageous that the toughness inverting input clock signal, whereby the Jitter of the store clock signal is reduced.

Embodiments of the invention are based on figures explained in more detail.

Show it:

Fig. 1 illustrates the principle diagram of the invention,

Fig. 2 shows an associated timing diagram,

Fig. 3 shows a variant for reducing the jitter and

Fig. 4 is an associated timing diagram.

The clock synchronization according to the invention shown in Fig. 1 contains a frequency divider 2 , which is fed via its clock input 1, a signal clock TS generated at the receiving end, whose frequency is approximately n times (n = 2, 3, 4,...) Data rate corresponds to a received digital signal DS. The frequency divider 2 is designed here as an asynchronous divider with three flip-flops 21 , 22 and 23 , which are triggered with the negative edge. There is a common reset input 4 through which the tilt stages 21 , 22 and 23 can be reset to the basic position (Q1 = 0, Q2 = 0, Q3 = 0). The digital signal DS is fed from an exclusive OR gate 5 (or exclusive NOR gate) and a delay element 6 (for example another gate) existing edge detector which generates a reset pulse RS on each signal edge. The divider output 3 is connected to the clock input of a sampling stage 8 , the data input D of which is also supplied with the digital signal. The equalized digital signal DSE is output at the output 9 of the sampling stage.

As already mentioned, the counter is reset to its basic position with each signal edge of the digital signal 7 . After three periods of the clock signal TS, the state of the store clock ET at the output 3 of the last flip-flop 23 changes . With this, the digital signal DS is stored in the sampling stage 8 and output via the circuit output 9 as a regenerated digital signal DSE.

A corresponding time diagram is shown in FIG. 2. If the digital signal DS is jitter-free (no edge distortion) and the frequency of the clock signal TS is exactly a multiple of the data rate of the digital signal DS, the counter 2 is only reset to its basic position once; the further reset pulses RS occur only periodically in these time ranges. Only when - due to the frequency deviations existing in practice - the phase deviations between the clock signal TS and the digital signal DS become larger, will a reset pulse not coincide with the basic position and reset the counter into it. This is indicated in Fig. 2 by the dashed line.

In the case of an edge-distorted digital signal (jitter), phase fluctuations in the reset pulse can also occur. Then the phase of the store clock signal ET also fluctuates accordingly. The smaller the number of flip-flops 21 , 22 and 23 of the counter 2 , the greater - in the unfavorable case - the phase fluctuations can occur even with small flank distortions of the digital signal. On the other hand, the frequency of the clock signal cannot be increased at will. The clock frequencies currently used are between approx. 70 and 280 MHz, clock frequencies up to 1 GHz and higher are possible. Although the counter 2 can be built up arbitrarily, because of the high clock frequencies, binary division ratios, for example dividers with 2 or 3 flip-flops, are particularly advantageous. Especially with asynchronous dividers, the runtime of the flip-flops must be taken into account and an additional runtime element may have to be inserted. In the case of binary dividers, the runtime to counter output 3 should ideally be half a clock period, then the digital signal is optimally sampled.

In Fig. 3 is a variant of the synchronization Darge provides, which also contains an Exclusive-OR gate 10 (or Exclusive-NOR gate) which is connected upstream of the clock input of the frequency divider 2 Fre. Furthermore, a gate 11 is provided, the first input of which is connected to an output Q1 of the first flip-flop 21 and the second input of which is supplied with the reset pulse RS. The gate 11 emits a pulse when the reset pulse does not fall within the range of the basic position of the frequency divider 2 H - that is to say also not in the basic position of the flip-flop 21 - and changes here due to the logic state at the output Q4 of a further flip-flop 12 , as a result of which the clock signal TSH at clock input 1 - designated TSH * - is inverted and its effective edge is shifted by half a clock signal period compared to the edges of the digital signal. The reset pulse must safely reset all flip-flops of the frequency divider.

Inverting the clock signal TSH results in a phase correction of the output signal by half a clock signal period. Compared to the solution according to FIG. 1, the divider therefore requires one divider flip-flop less at a frequency of the clock signal that is smaller by a factor of 2. In addition, since the relevant clock edge is shifted relative to the edges of the digital signal DS, the jitter of the memory clock ET is significantly reduced.

With larger flank distortions, of course, it also happens this variant on phase fluctuations of the memory clock.

An additional way to incorrectly reset the Avoid frequency divider in case of strong jitter given a counting device that is only at least two in reset pulses falling the same frequency division Resets the frequency divider.

In the associated timing diagram of Fig. 4, the same synchronization process is shown. By a reset pulse RS falling here in the most significant state Q1 = 1, Q2 = 1 of the frequency divider 2 H, the clock signal TSH is inverted, as a result of which its first effective edge and the further effective edges come earlier and also the effective edge of the memory clock signal ET is emitted earlier becomes.

The synchronization can both with synchronous frequency parts learn (Johnson) as well as with asynchronous, variants of the logic circuits can also be provided become.

Claims (6)

1. Digital clock synchronization for a digital signal (DS), in which an adjustable frequency divider working at the n-fold frequency of the digital signal (DS) outputs a memory clock signal (ET) at its Tei ler output ( 3 ) with which the digital signal (DS) in a scanning flip-flop ( 8 ) is temporarily stored,
characterized by
that the frequency divider has a reset input ( 4 ),
that an edge detector ( 5, 6 ) is provided, the output of which is connected to the reset input ( 4 ) and the input of which is supplied with the digital signal (DS),
that the edge detector ( 5, 6 ) when the state of the Digi talsignal (DS) outputs reset pulses (RS), the frequency divider in its basic position (0, 0, 0) reset, and
that the store clock signal (ET) gives an effective pulse of the store clock signal (ET) after about half a period of a message step of the digital signal (DS). 2. clock synchronization according to claim 1, characterized in that an exclusive OR gate ( 5 ) / exclusive NOR gate is provided as an edge detector ( 5, 6 ) with a delay element ( 6 ) switched on between the inputs thereof. 3. clock synchronization according to claim 1 or 2, characterized in that in the signal path of the clock signal (TS), a clock signal derived therefrom or the memory clock signal (ET), a further delay element ( 13 ) is switched on. 4. clock synchronization according to one of the preceding claims che,  characterized, that a frequency divider with a division ratio "n" from 4 to 8 is provided. 5. clock synchronization according to one of the preceding Ansprü surface, characterized in that the clock input ( 1 ) of the frequency divider is preceded by an exclusive OR gate ( 10 ) / exclusive NOR gate, the first input ( 1 a) of the clock signal (TS ) is supplied and the second input is supplied with a control signal, the logic state of which is changed when a reset pulse (RS) occurs outside the basic position of the frequency divider. 6. clock synchronization according to claim 5, characterized in
that a further gate ( 11 ) is provided which links the reset pulse (RS) and the logic signal of an output (Q1) of the first flip-flop ( 21 ) of the frequency divider by an AND function and
that a further flip-flop ( 12 ) is provided, the clock input of which is connected to the output of the further gate ( 11 ) and an output (Q4) of which is connected to the second input of the exclusive OR gate ( 10 ) / exclusive NOR gate connected is.