SU746895A1 - Device for synchronizing monitor and standard digital signals - Google Patents

Description

The invention relates to a pulse technique and can be used in control · / measuring equipment for. digital communication systems and computer technology. . 5

By main auto No. 598226, a device is known for synchronizing control and reference digital signals, comprising a clock counter, a _t- encoder, a clock frequency allocation unit, a reference signal generator; block of mismatches, prohibition schemes, trit-ger, two coincidence elements and an inverter. ~ ₁₅

The disadvantage of the device is that the duration of the cycle of comparing the control and reference pulse sequences does not depend on in which cycle cycle the first mismatch _{w is} detected. This leads to a relatively long time to enter synchronism.

The aim of the invention is to reduce the synchronization time.

. 2 ''. ''

This goal is achieved by the fact that in the device for synchronizing control and reference digital signals containing a prohibition circuit, a clock allocation unit, the input of which is connected to the control signal bus, the first output of the clock allocation unit> is connected to the Clock Counter input, whose outputs are connected through a decoder to the first inputs of the first and second coincidence elements, the output of the second coincidence element is connected to the first input of the reference signal generator, second. A swarm input of which is connected to the output of the Clock allocation block, an inverter, a Trigger, and a mismatch block, the output of which is connected to the first input of the inhibit circuit, the second input of which is connected to the last bit of the clock counter, and the output of the inhibit circuit is connected to one of the trigger inputs, the other whose input is connected to the second output of the decoder, and the output of the trigger is connected to the second input of the second element '3 g ^- ? ¹ 7? OTHERWISE DEPOS ^ also through the Inverter with the second input of the first coincidence element, the output of which is connected to the third input of the reference signal generator, the output of which is connected to the first input of the mismatch unit, the second input of which is connected to the control signal bus, the inverter is additionally introduced, included between the output of the last digit of the counter, clocks and the input of the inhibit circuit, and the output of the inhibit circuit is connected to the installation input to zero of the clock counter. The functional diagram of the device is shown in the drawing and structurally contains a clock counter 1, a decoder 2, a clock allocation unit 3, a reference signal generator 4, a mismatch unit 5, a ban circuit 6, a trigger 7, coincidence elements 8 and 9, and inverters 10 and 11. The device works as follows.

. In block 5 of mismatches, a bitwise comparison is made of the control 25 which clock shows the first mismatch of the signal coming to the input of the C line device and the reference signal, the formation of mismatches is completed when the generator detects 4. The detected non- match is detected by trigger 7 and. ·. · Sets 1 counter to 'zero * COO-being ^{of 30,} the signal output from the inversion, the torus 11 closes prohibition circuit 6, 7 by disabling trigger output unit 5 mismatches. Then the signal from the output of 'a;

decoder 2 is read through element ³⁵

746895 4 prohibition circuit 6 is opened, and a new synchronization cycle begins, repeating until after 2 ⁿ ' ¹ clock there are no mismatches (n is the number of bits of the counter). If there are no mismatch cycles for 2 ^П * ^{4, the} trigger 7 remains zero, and the signal from the output * a * of the decoder 2 through the coincidence circuit 8 enters the generator 4 circuit, fixing the end of the synchronization process. The last (n-th) digit of the counter ensures that trigger 7 is disconnected from block 5 of mismatches for the time necessary for! completion of transients caused by the shift of the reference sequence by a clock, and also allows you to separate in time the recording of mismatches, their reading and the return of the trigger to its original state, necessary for the stable operation of the device. In the known device, the cycle of detection of discrepancies continues for 2 cycles and does not depend on B | nie. In this device, the cycle reveals the first mismatch. Thus, by reducing the length of the cycle for detecting discrepancies, the overall time to enter synchronism is reduced.

Claims (1)

The invention relates to a pulse technique and can be applied in the control-measuring apparatus for. digital communication systems and computing. . According to the main and BT. St. No. 598226, a device for synchronizing a reference reference digital signals, comprising a clock counter, a decoder, a clock frequency selection generator, a reference signal generator; block mismatch, prohibition scheme, trigger, two elements of the match inverter. The disadvantage of the device is that the duration of the comparison cycle of the control and reference sequence; these pulses do not depend on which cycle cycle is affected by the first mismatch. This leads to a relatively long time to synchronization. The goal of the invention is to reduce the synchronization time. This goal is achieved by the fact that ITO into the device for synchronizing control and standards of digital signals, containing a prohibition scheme, a clock selection unit, whose input is connected to the bus signal, the first output of the clock selection unit, which is decoder connected to the first inputs of the first second element of the match, the output of the second element of the match is connected to the first input; home of the reference generator, the second input of which is connected to the output of the clock selection unit, the inverter, the trigger mismatch block, the output of which is connected to the niepBbtM input of the inhibit circuit, the second input of which is knockHeH to the last bit of the clock counter, and the output of the inhibit circuit is connected to one of the trigger inputs, the other input of which is connected to the second output of the remote controller, the output of the trigger is connected to the second input of the second element of the {{T; Shadbershör6) means and through the inverter with the second input of the first element is the same and, the output of which is connected to the third input of the generator of the reference signal, the output of which is connected to the first input of the mismatch block, the second input of which is connected to the luHjfie of the control signal, the inverter connected between the output of the last bit of the clock counter and the input of the inhibit circuit, and the output of the circuit the ban is connected to the input of the zero setting of the TakToa counter. The functional diagram of the device is shown in the drawing and constructively contains a counter of 1 cycles, a decoder 2, a block 3 for allocating a clock frequency, a generator 4 the reference signal, the block 5 fails, the prohibition scheme 6, the trigger 7, the elements 8 and 9 and the inverters 10 and 11. The device operates as follows. . In block 5 of mismatches, a one-by-one comparison of the control signal arriving at the input of the device from the line, - and the Reference signal generated by the generator 4 is performed, and the Nose detection is detected by the trigger 7 and sets the counter 1 to zero connection, and the signal from the output of the inverter ; torus 11 closes scheme 6 zareta, disconnecting t | pgger 7 from block 5n outgoing; b; Then, the signal from the output of the decoder 2 is read through the element 9 and falls into the generator 4 circuit, shifting the reference sequence per clock. After the termination of the trigger of the 7th output of the decoder 2, an impulse trigger is created, which prepares it for a new sync sync pattern. In case of a low bit of 1 clock cycle b, the single blocking scheme 6 of the prohibition opens, and a new synchronization cycle starts, repeating until a mismatch is detected per cycle (GA is the number of counter bits). If there are no mismatches during the cycles, the trigger 7 remains zero, and the signal from the output of the decoder 2 through the coincidence circuit 8 enters the generator circuit 4, fixing the end of the synchronization process. The last (nth) counter bit disables trigger 7 from block 5 mismatches for the time required to complete the transient processes caused by the shift of the reference sequence per cycle, and also allows you to split in time fixes mismatches, read them and return the trigger to its original state necessary for SUSTAINABLE operation of the device. In the known device, the cycle you left off the mismatch lasts for 2 cycles and does not depend on B | The tact is the first mismatch. In this device, the cycle of detection of discrepancies is completed when the first failure is detected. In this way, by reducing the duration of the cycle for eliminating mismatches, the overall synchronization occurrence is reduced. The invention is invented by | N1i. A device for synchronization of a co-control and a reference digital SIGNAL according to the author. No. 598226, whether it is at 9, C by the fact that, in order to reduce synchronization times, an inverter is connected to it additionally connected between the output of the last bit of the clock counter In the input of the inhibit circuit, and the output of the inhibit circuit is connected to the input of the BOBicH device in the counter clock.