SU1603386A1 - Device for checking digital units - Google Patents

Abstract

The invention relates to computing and can be used as an embedded control tool in the composition of diagnostic systems of computer systems. The aim of the invention is to increase the reliability of the control. The device contains a generator of 1 tests, a signature analyzer 2, a unit 3 of comparison, a group of switches 4.1. 4.K. In the device, in the control mode, from the outputs of the monitored block, the sequence of signals is fed to the inputs of the signature analyzer 2, and instead of these sequences, the sequences of binary signals from the outputs of the generator 1 are received at the corresponding contacts of the monitored module connector.

Description

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The invention relates to computing and can be used as an embedded means of controlling digital devices, in particular, in the composition of diagnostic systems for computing systems.

The purpose of the invention is to increase the reliability of the control.

Lig.1 shows the block diagram of the device; 2 is a block diagram of a comparison block.

The device contains a test generator 1, a signature analyzer. 2, comparison unit 3, switches 4. FIG. 1 also shows the monitored unit 5 and the connector 6 of the structural module in which the device is used, the information inputs 7 of the monitored unit 5, the information outputs 8 of the monitored unit 5, which are information inputs

8 devices, information outputs

9 devices, device start input 10, device clock input 11, device control time setting inputs 12, device reference reference inputs 13, block mode output 14, output block 15 output outputs 15, device control output output 16, device transfer control output 17 - properties.

Block 3 contains a group of elements OR 18, a group of adders 19 by mol two, delay element 20, element OR 21, trigger 22, element AND 23, element OR 24, delay element 25, counter 26, element 27, delay element 28, element And 29, element 30 delay.

The device operates in a manner.

At start input 10, a start signal is received.

enters I, setting control mode. This pulse arrives at the installation input into state 1 of trigger 22, setting signal 1 at its output, and simultaneously at the second input of the OR 21 element, and from its output at the second input of the AND 23 element. At the third input of the And 23 element, clock pulses input 11, to the first input - signal 1 from the inverse output of the element AND- 27. From the output of the element And 23 a pulse arrives at the input of the element 25 of the delay, and from its output to the first input of the element OR 21. Until then.

five

0

until the first input of the AND 23 element comes from the inverse output of the AND 27 element, signal 1, the output of the AND 23 element is each pulse appears pulse. This pulse every clock is fed to the counting input of the counter 26. The counting module of the counter 26 determines the delayed signal output

Q control of the transfer of the result by block 3. The counter counting module can be reduced by eliminating the higher bits of the counter from the account as a result of continuously supplying the values of signal 1 through the corresponding inputs 12 to the first inputs of the elements OR 18, and the decrease will be the greater, the more the number of elements OR 18 will be constantly signaled 1.

When a predetermined state of the counter is reached, when signals 1 are present at all inputs of the And 27 element, then And 27

5, signal 1 appears, and on the inverse, signal O, which arrives at the first input of element And 23, prohibits the passage of signals in the circuit of elements 21 and 23, i.e stops

0 the supply of pulses from the output of the element 23 to the counting input of the counter 26. At the same time, the signal 1 from the direct output of the element 27 is fed to the reset input of the trigger 22 and sets at its output a signal O indicating the operating mode.

The signal 1 from the direct output of the element And 27 enters the input of the element 28 / delay for one cycle, from its output - 0 to the input of the element 20 delay for one cycle and after a cycle from the output of the delay element 20 enters the reset input of the counter 26 and sets to its outputs are signals of O by preparing the count 5 to 26 for the next control session.

When the signal O, meaning the operating mode, coming from the output 14 of the mode 3 of the block to the control inputs of the switches 4, is allowed to propagate the sequences of signals from the information inputs 8 of the device to the information outputs 9 of the device, i.e. the information outputs 8 of the monitored block 5 5, connected to the corresponding information inputs 8 of the device and the corresponding first information inputs of the switches 4, are connected to the first outputs

five

switches 4 and their corresponding pins 6

When the control inputs of the switches 4 from the output 14 of the block 3 in the control mode arrive at the signal l, the signals from 1) of the device inputs 8 of the device to cr .vrBe4CTByioqHe inputs of the multiple-pass signature analyzer 2, i.e. information zykhods 8 of the monitored block 5, connected to the corresponding inbury inputs 8 of the device and to the corresponding km first information inputs of the switches 4., are connected to the second outputs of the switches 4 and to the corresponding inputs of the multiple input signature analyzer 2. At the same time, -i ry informational inputs of KOMi-iyTa TO-ryov 4 from the corresponding outputs of the generator 1 of the test, the test sequence is fed from the first outputs of the switches to the corresponding information zykhody 9 devices, i.e. the outputs of the test generator 1, connected to the second information inputs of the switches 4, are connected to the first outputs of the switches 4 and to the corresponding contacts of the connector 6.

The information inputs 7 of the monitored block 5 in the lattice control from the corresponding contacts of the connector 6 receive a test sequence generated outside this structural module (in another (other) structural module (modules)). The number of switches in the device is one less than the maximum possible amount of information inputs 7 and outputs 8 of the monitored unit 5, equal to the number of signal contacts of the connectors of the structural modules in which the device is located.

The number of 7 in the involved switches of the device is equal to the number of information outputs 8 of the block 5 of the concrete design module, the device is placed in the bushing. For non-active switches 4 devices, the main, first and second information inputs and the first outputs provide a circuit signal O., and the second outputs are connected to the corresponding inputs of block 2,

The test generator uses a number of outputs equal to the number of switches involved.

 In the control mode, the signal 1 from the output of mode 14 of block 3 is fed to the input of the generator 1, sets the output mode of test kits, and to the input of the signature analyzer 2, and sets the signature generation mode. From the test generator outputs connected to the second information inputs of switches 4, the test sequences are fed in control mode 15 to the output contacts of the connector, and the corresponding inputs of the multiple input signature analyzer 2 receive the output sequence of the monitored unit 5, 20 converted into a multiple input signature analyzer into the resultant the signature that comes from the outputs 15 to the inputs of the adders to the module two, the first inputs of which are 25 connected to the inputs 13 of the reference signature to which The circuit constant values 1 and O, corresponding to the reference signature, are supplied. When all the bits of the reference and the resulting signatures coincide, all the inputs OR 24 receive the signals O, the output of the OR element 24 appears the signal O, indicating the operability of the monitored device. If the signatures do not coincide at least in one bit, a signal 1 appears at the output of the IPI 24 element, indicating a malfunction of the monitored device that arrives at the second input of the And 29 element.

The signature generation in the signature analyzer 2 is completed with the termination of the signal 1 at 5 output 14 of the block 3, and with the moment of completion of the signature generation the timing of the test sequence supply by the generator 1 is matched. Alternator 1 and 0 are synchronized from the device's clock.

The signal 1 from the direct output of the element AND 27 enters the input of the delay element 28, from the output of output, to the input of the input element 30 of the delay and to the first input of the element 29, allowing the output of the control unit 3 to output 3 of the output of the OR element 24 control result signals.

also to the input of the element 20 delay, the output of which is to the reset input of the counter 26.

After a cycle of occurrence of the result signal at the output 16 of the output of the delay element 30, the signal arrives at the output 17 of the transmission control of the result of block 3 as a control signal necessary to begin the process of transmitting the monitoring result signals to the output of the diagnostic system, which includes the monitoring device . The delay of the control signal for a given time interval relative to the result signal, for example, one clock cycle, as implemented in the device, is necessary so that the result signal during this time interval can be recorded in the device intended for its transmission, and in the following tact without distortion transmit.

Claims (2)

1. A device dp of controlling digital blocks containing a test generator, a comparison unit and a signature analyzer, the device clock input being connected to the clock inputs of the test generator and signature analyzer, the outputs of the resulting signature of which are connected to the inputs of the resulting signature of the comparison unit, the first and second outputs of which are outputs of the result of monitoring and controlling the transfer of the result of the device, respectively, characterized in that, in order to increase the reliability of the control, the device contains a group of switches, where the group of inputs of the device reference signature is connected to the group of inputs of the reference signature of the comparator unit, the clock input and the start input of which are connected respectively to the clock input and the start input of the device, the group of time control inputs is connected to the inputs of the time control of the comparison unit, the mode output of which is connected to the trigger inputs of the test generator, the signature analyzer, and the control inputs of the group switches, the first information each entrance connected to the same information input of the device to connect to the same information output of the monitored unit, the second information input of each switch of the group is connected to the same output of the test generator, the first output of each switch of group 0 is connected to the same output of the group of information outputs of the device, the second outputs of the switch of the group connected to a group of like inputs of the signature analyzer. five 2. A device according to claim 1, characterized in that the comparison unit comprises a group of modulo two adders, two elements OR, three 0 element AND, a group of elements OR, four delay elements, a trigger and a counter, with the first inputs of modulators two groups connected to the same inputs of the standard block signature, each input of which control time is connected to the first input of the same element OR group, the second inputs which are connected to the outputs 0 of the first group of outputs of the counter, the second group of outputs of which is connected to the inputs of the first element And, the direct output of which is connected to the input of the first delay element, the output of which is connected to the inputs of the second and third delay elements and to the first input of the second element And whose output is output of the control result of the block, control output 0 the transfer of the result of which is the output of the second delay element, the reset input of the trigger is connected to the forward output of the first element AND, the inverse of which is connected to 5 the first input of the third element And, the output of which is connected to the counting input of the counter and through the fourth delay element with the first input of the first element SH, whose output 0 is connected to the second input of the third element I, the third input of which is connected to the clock input of the block and to the corresponding input of the first element AND, the outputs of the elements OR are connected to the corresponding inputs of the first element AND, the second inputs of the modulators are two groups connected to the input group of the resulting signature block outputs modulo two groups connected to the inputs of the second element OR, the output of which is connected to the second input of the second element And the input start block is connected to the second input of the first element This OR with a single trigger input, the output of which is the output of the block mode, the code of the third control element is connected to the reset input of the counter.