SU489234A1 - Device for detecting address code - Google Patents

Description

(54) DEVICE FOR DETECTING ADDRESS CODE

one

The invention relates to asynchronous address communication systems (LAOS) with time-frequency coding (PMC) and can be used in telemetry and radio control systems.

A device for detecting an address code is known comprising a series-connected high-frequency amplifier and an input signal transforming and dividing unit, the outputs of which are connected to the inputs tl of the channels, each of which consists of a series-connected multiplier, a reference-controlled local oscillator, an integrator and a threshold node a control input through which a series-connected unit for generating a control voltage and a unit for generating a response threshold is connected to an output an input pulse pulse of the possible time position of the useful pulse, to the input of which the input of the multiplier is connected, which is also the input of the channel.

However, the known device has a low noise immunity.

The aim of the invention is to improve the noise immunity of the device.

For this, a meter of amplitudes of mixing and useful pulses is inserted into each channel, with the second input of the unit connected to the multiplier input to form a control voltage through a meter of the ratio of amplitudes of the bias and useful pulses, to the control input of which and to the second input of the meter of the overlap interval A pulse of the possible time position of the useful pulse is connected to the local oscillator output of the reference signal.

On the chetzhe there is a structural electric drive unit diagram.

Claims (1)

The device for detecting the address code contains a high frequency amplifier 1 and a node for converting and dividing the input signal 2, the outputs of which are connected to, are connected to the inputs tl of the channels (where fl 1,2, ...), each of which consists of series-connected multipliers 3, a heterodyne-controlled reference signal 4, an integrator 5 and a threshold node 6, to the control input of which, via a serially connected unit, to generate a response threshold 7 and a unit to form a control on yarn 8, the output of meter 9 int is connected The interval of overlap by the input pulse of the possible temporal position of the useful signal, to the input of which is connected the input of multiplier 3, which is also the input of the channel, as well as the input of the unit for shaping the control voltage 8 through the amplitude ratio meter 10 to The second input of the $ 1 span of the overlap 9 is connected to the output of the local oscillator of the reference signal 4. The device operates as follows VIBRATION after amplification by a common high-frequency amplifier 1, conversion and separation of the input with the signal by node 2 is fed to the H frequency channels of the device to detect the address code of the AACC receiver with the PMCs. In each channel at the moment of a drift of a useful pulse in multiplier 3, the input and reference signals are multiplied, then the output voltage is generated by the integrator 5. This is ensured by the fact that the reference oscillator 4 opens with the first pulse from the receiver decoder only for the time of arrival useful impulse. The output voltage supplied to the threshold node of the biv in the presence of a useful pulse must exceed the voltage of the triggering threshold Uj, fixing its presence. In each channel, the suppression of the useful pulse interfering with the voltage U; is reduced due to the fact that between the input of the multiplier 3 and the additional one: the input of the unit for forming the response threshold 7 is connected in series with the meter of the overrun interval by the input pulse of the possible time position of the field pulse 9 and the unit for generating control voltage 8. However, the device for detecting An address code operating in a large dynamic range is most affected by signals from closely located transmitting transmitters, which lead to the formation of spurious addresses. oh codes. Suppression of spurious address codes can be achieved if in each frequency channel of the receiver between the input of multiplier 3 and the unit for generating control voltage 8 in parallel with the overlap interval meter 9 input pulse of the possible time position of the useful pulse, turn on the amplitude ratio of the moving and useful pulses 10, V as a result of imposing a pacing pulse on a possible temporal position of a pre-exposure pulse, which leads to the formation of a false pulse, the voltage U. increases and The pulse is suppressed. Apparatus of the Invention A device for detecting an address code, comprising a series-connected high-frequency amplifier and a node for converting and separating an input signal, whose outputs are connected to the inputs of the P channels, each of which consists of a series-connected multiplier, a local oscillator-controlled reference signal, an integrator and a threshold a node to a controllable input of which through a series-connected unit for generating a control voltage and a unit for generating a response threshold The output of the overlap interval meter is switched on by the input pulse of the possible time position of the useful pulse, to the input of which a multiplier is connected, which is also a channel input, characterized in that, in order to increase the noise immunity, an offset ratio of the bias pulse and the useful pulse is inserted into each channel, and The input of the multiplier is connected to the second input of the unit for generating a control voltage through a metering ratio of the amplitudes of the billing and useful impulses, to the control input of which A second output signal of the reference oscillator is connected to the second input of the interval overlap by the input pulse of the possible time position of the useful pulse.