SU1697213A1 - Device for pulse-width-to-analog signal conversion - Google Patents

Abstract

The invention relates to electrical engineering. The aim of the invention is to improve the accuracy and speed in a wide range of variation of the frequency of the input signal. Pass the threshold element 1 latitude Pulse oscillations of an improved form are fed to one input of the element 6, to the other input of which a signal is received from the output of the generator 5 quantization pulses. The frequency of quantization pulses f is 2N times the frequency of the input signal F, i.e., -P. This frequency ratio is maintained in the entire allowable frequency range of the input signal using phase comparator 3, smoothed by the filter — low frequency 4, the output signal of which is used to automatically adjust the frequency of the quantization pulse generator 5. At the output of element 6, a packet of quantization pulses is generated, arriving at the clock input of the counter divider by 2-7, the code from which, having passed through the digital-to-analog converter 8 and the scaling amplifier 9, is converted into an analog signal. At the end of the counting of the number of pulses in a packet, the value of the output signal of the scaling amplifier 9 is stored in the sampling device 10 and is crimped and appears at the output of the device being injected. 2 Il.

Description

The invention relates to electrical engineering and radio engineering and can be used as a functional converter of pulse-width oscillations into an equivalent analog signal.

The aim of the invention is to improve the accuracy and speed in a wide range of variation of the frequency of the input signal.

FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagrams of his work.

The device (Fig. 1) contains a series-connected threshold element 1, a counter-divider by 2 2. phase comparator 3, a low-pass filter 4, a generator of 5 quantization pulses, an And 6 element, a counter-divider by 2N 7, a D / A converter 8 , a scaling amplifier 9, a device 10 for sampling and storage, as well as a counter-divider for 2 11, an input connected to the generator 5 output of quantization pulses, an output to the second input of the phase comparator 3, a driver 12 sampling pulses, input

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connected by the output of the threshold element 1 and the second input of the element 6, the output to the control input of the device 10 for sampling and storage, the delay element 13 connected to the output of the driver 12 for the sampling pulses, the output for the installation of the divider counter O on.

The device works as follows.

The input signal in the form of two-pole pulse-width oscillations with frequency F and duty cycle Q (FIG. 2a) is fed to the input of threshold element 1, which increases the steepness of the front and fall of the input pulses and turns them into unipolar with the necessary for normal operation of digital circuit elements amplitude (Fig. 2 b). The pulse-width oscillations of the improved form are fed to the input element Ib, to another input of which a signal is received from the output of the generator 5 quantization pulses (Fig. 2c). The frequency of quantization pulses f is 2N times the frequency of the input signal F, i.e.

.

This frequency ratio is maintained over the entire allowable frequency range of the input signal using phase comparator 3, the output signal of which is smoothed by low-pass filter 4, is used to automatically adjust the frequency of the generator 5 quantization pulses. The divider counter by 2 2 excludes the influence of the duty cycle of the input pulses on the operation of the phase comparator 3, and the divider counter by 2N + 1 11 serves to Reduce the frequency of the generator 5 quantization pulses to the frequency of the signal at the input of the phase comparator 3. At the output of the And 6 element a packet of quantization pulses (Fig. 2 g) is formed, arriving at the clock input of the counter divider by 2 7, at the output of which a parallel binary normal code is obtained corresponding to the number of pulses in the packet. This code is fed to the input of the N-bit digital-to-analog converter 8 of a parallel binary normal code, as a result of which the output of the scaling amplifier 9 has an analog signal (Fig. 2 d). After the counting of the number of pulses in the packet (by the input signal decay), the output signal of the scaling amplifier 9 is stored in the device 10 for sampling and storage and appears at the output of the device to be injected (Fig. 2e). The control signal to the sampling and storage device is generated by the shaper of 12 sampling pulses (fmg. 2 g) from the decay of the input

signal. The duration of the sampling pulse is not less than the sampling and storage device sampling time and not less than the installation time in O of the divider counter by 2N 7.

The sampling pulse is delayed by the delay element 13 for the duration of the aperture time of the sampling and storage device 10 and then used to set the O divider counter at 2 7.

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Claims (1)

Claims An apparatus for converting pulse-width oscillations into an analog signal comprising a low-pass filter 5 quantization pulse generator, a series-connected N-bit parallel digital-to-analog converter and a scaling amplifier, characterized in that 0 increase the accuracy and speed in a wide range of input frequency, it is equipped with a threshold element, a counter-divider by 2, a phase comparator, a counter-divider 5 by 2 +, element I. by a counter-divider by 2, a sampling and storage device, a pulse shaper of the sample and a delay element, with the input of the threshold element designed for connecting to 0 to the input source, and the output of the sampling and storage device to the output consumer, the output of the threshold element is connected to the clock input of the counter divider by 2, the input of the driver 5 sampling pulses and the first input of the element I, the first input of the phase comparator is connected to the output of the counter-divider by 2, and the second input to the output of the counter-divider by 2 m + 1 output of the phase comparator 0 is connected to the input of the low-pass filter, the output of which is connected to the input of the frequency control of the quantization pulse generator 2N times the frequency of the input signal, the second input of the AND element 5 is connected to the output of the quantization pulse generator and the clock input of the counter-divider on 2N41, the output of the And element is connected to the clock input of the counter-divider on 2, N parallel outputs of which 0 is connected to the corresponding information inputs of the digital-to-analog converter of the binary normal code, the output of the scaling amplifier is connected to the analog input of the sampling and storage device, the control input of which is connected to the output of the sampling driver and the input of the delay element 2N connected to the output of the delay element. oh entrance E 3- / Lho 3 W l /g./ Sh-w $ exit