SU731574A1 - Pulse-width modulator - Google Patents

Description

The invention relates to the field of coding and information conversion and can be used in automation devices and computer technology.

Known pulse-width modulator containing pulse counters, a counting trigger with AND elements and a code rewriting circuit that provides a linearly varying duty cycle of the output pulses depending on changes in the input voltage [1].

The disadvantage of the modulator is that it does not provide the formation of pulse durations as a function of the average value of the control signal within one period, and the formation of the pulse width proportional to the integral of the input voltage over several periods, which reduces the accuracy of the conversion of the input signal.

Known pulse-width modulator containing a clock, a sawtooth generator, a comparator, trigger, valve, key and capacitor of constant capacity [2].

The time interval at the output of this modulator is proportional to the integral of the input voltage over several switching periods. However, the disadvantage of this modulator is the low stability and accuracy associated with the accumulation of error on the integrating capacitor of the modulator.

The purpose of the invention is to improve the accuracy and stability of the conversion of the input signal by a pulse-width modulator.

This goal is achieved by the fact that an analog-to-digital converter is introduced into the modulator, which contains a clock generator and a comparator, accumulating an adder and a pulse counter, the clock generator being connected to the clock input of the analog-to-digital converter and to the pulse counter input, the bit outputs of which are connected to the inputs of the comparator, and the output of the highest order is connected to the enable input of the accumulating adder, the remaining inputs of the comparator are connected Res accumulator outputs from the analog-digital converter whose input is connected to the input device, outputs of which are connected to the outputs of the pulse counter, comparator and accumulator significant yield.

about

The drawing shows a functional diagram of a modulator.

The pulse-width modulator contains a clock pulse generator 1, the outputs of which are connected to the clock input of the analog-to-digital converter 2 and the input of the counter 3, the outputs of the analog-to-digital converter through the accumulating adder 4 are connected to the inputs of the comparing device 5, to the other inputs of which the discharge outputs of the counter are connected 3, and the output of its senior discharge is connected to the output 6 of the device and the enable input of the accumulating adder 4, the sign output of which is connected to the output 7 of the device, and the output compare device 5 is connected to the output 8 of the device.

The proposed device operates as follows.

The clock generator 1 generates square-shaped pulses arriving at the converter 2 and at the binary counter 3. At the moment the counter passes through "O", pulse U \ appears at its output 6, corresponding to the beginning of the time interval. Pulses follow with a repetition period of T = 1 \ -2 ^m , where T \ is the repetition period of the clock pulses of generator 1; M is the number of bits of the counter 3. Converter 2 converts the input signal U (ί) of variable magnitude and sign into a binary parallel LA-bit code. An additional ^ + 1-bit converter carries information about the sign of the input signal U (7). From the outputs of the converter 2, the code combination is fed to the inputs of the accumulating adder 4, which consists of the actual 77 + 1-bit adder and a memory block of L / + 1 bits. The discharge 77 + 1 in the accumulating adder 4 is significant. The accumulating adder 4 integrates the digital signal coming from the output of the converter 2. The information at the output of the accumulating adder 4 remains unchanged for a time T and changes only when the pulse U _it arrives from the output of the counter 3 pulses.

Thus, at time t - - Ti, where i - 1, 2, ..., at the output of accumulating adder 4, a code combination Yi is formed corresponding to the approximate value of the input voltage integral U (7) _r = k ₀ + 2 ^ to.

K = 1 where Y _o is the code combination corresponding to the initial value of the Po integral;

X _to - code combination corresponding to the value of the input voltage U (V) at time t = T _fi , for k ~ \, 2, ..., i.

When the accumulating adder 4 is overflowed, the X-bit transfer signal sets, with the arrival of the pulse Ui, all code bits in the accumulating adder to the “1” position.

The code combination from the output of the accumulating adder 4 is supplied to the inputs L ^; -discharge comparison device 5, to the other inputs of which a code combination is supplied from the outputs of the pulse counter 3. At the moment of coincidence of the code combinations, the comparison device 5 generates a pulse U ₂ corresponding to the end of the time interval which is output to the device output 8.

Then the duration of the time interval generated by the device at the t-th moment of time is determined by the expression which represents the approximate value of the integral 'o - K' (t) dt + U ₀ , о

where K is the scale factor of the approximate integration method.

The proposed device provides high accuracy and stability of the conversion of the input voltage into a pulse-width signal, and when used in amplifiers, reversible voltage regulators, measuring devices will improve their operational characteristics.

Claims (2)

1. USSR author's certificate number 415795, cl. N OZK 7/08, 08.16.71. 2. USSR author's certificate number 308500, cl. H OZK 7/08, published. 1971. aUj fL P Jl