RU2171011C1 - Pulse-width modulator - Google Patents

Abstract

FIELD: radio engineering. SUBSTANCE: pulse- width modulator is related to electrical circuits of time-pulse converters. It can find use in design of mixed-signal instruments and computers. In proposed pulse-width modulator demodulation of output pulse-width signal with time division of stages of conversion process is carried out in feedback circuit which excludes error caused by actual values of passive components included in mix of device. Modulator has generator 1 of synchronizing pulses, reference voltage source 2, comparator 3, first key 4, integrator 5, retrieval and storage unit 6, pulse distributor 7, second key 8 and digital accumulating former 9 of pulse- width signal. Output of first key 4 is connected to input of integrator 5 whose output is linked to information input of retrieval and storage unit 6. Output of reference voltage source 2 is connected to input of first key 4. Output of retrieval and storage unit 6 is tied up with information input of second key 8 and with inverting input of comparator 3 whose noninverting input is input of pulse-width modulator. Output of comparator 3 is connected to information input of digital accumulating former 9 whose output is output of pulse-width modulator integrated with synchronization input of pulse distributor 7. Three outputs of the latter are connected to controlling inputs first key 4, second key 8 and retrieval and storage unit 6. Outputs of keys 4 and 8 are tied up together and output of generator 1 of synchronizing pulses is connected to input of digital accumulating former 9. EFFECT: increased operational accuracy of modulator with simultaneous simplification of its design. 4 dwg

Description

 The invention relates to electrical circuits of pulse-width modulators and can be used in the construction of mixed-signal measuring devices and computing devices.

 There are a large number of pulse-width modulators, a generalized scheme of which is described in [1, p. 137-139]. The disadvantage of all such devices made according to the scattering scheme is the presence in the composition or requirement of an external generator of the scattering signal, the accuracy of the converter largely depends on the parameters of which.

 According to a more efficient, from the point of view of accuracy and noise immunity, the following circuit is implemented device [2, p. 51]. It can be used for pulse width modulation in conjunction with a pulse width modulated (PWM) sequence generator based on a binary code. Its disadvantage is the low accuracy due to the use of a resistive digital-to-analog converter, which does not provide high resolution for low bit depth, and high accuracy and linearity for high bit depth.

 Of the analogues, the closest in technical essence is the solution described in [3]. Considered a pulse-width modulator and is selected as a prototype. The prototype has a higher accuracy compared to the device [1] due to the fact that it is designed as a tracking device and does not need a generator of a deployment signal. In addition, in the feedback of this device there is no resistive digital-to-analog converter that does not allow for high accuracy, as in the device [2].

 The prototype includes a synchronizing pulse generator (GSI), a reference voltage source (ION), a comparator, a key, a first algebraic adder and a multiplier, and the output of the key is connected to the information input of the first integrator, the output of which is connected to the information input of the UVX, the input signal goes to the information input of the second integrator, the output of which is connected to the second input of the comparator, the ION output is connected to the information input of the third integrator, whose output is connected to the first input of the multiplier, the first input q the comparator is connected to the output of the multiplier, and the output is to the information input of the key, the output of which is the output of the device, the output of the first integrator is connected to the first input of the algebraic adder, the second input of which is connected to the output of the I / O, and the output is connected to the second input of the multiplier, the output of the ICG is connected to the control inputs of the first, second and third integrators, as well as the key and the I / O.

 The prototype converts the input voltage into a PWM signal according to a linear law.

 The disadvantage of the prototype is low accuracy, since, according to the condition of conversion, the time constants of all three integrators must coincide and be equal to the period of the synchronizing pulses at the output of the GSI. Ensuring this condition is a significant difficulty, and the conversion will contain an error due to the actual values of the parameters of the passive components that make up the integrators.

 The technical result of the invention consists in improving the accuracy of the pulse-width modulator while simplifying the device.

 The objective of the invention is the creation of a pulse-width modulator, in the feedback circuit of which the demodulation of the output PWM signal is carried out with time separation of the stages of the conversion process. This eliminates the error due to the actual values of the passive components that make up the device.

 The problem is solved by creating a device containing a GSI, ION, a comparator, a first key, an integrator, a CVC, a pulse distributor (RI), a second key and a digital accumulating driver of a PWM signal (TsNF), the output of the first key being connected to the integrator input, the output which is connected to the information input of the UVX, the ION output is connected to the information input of the first key, the output of the UVX is combined with the information input of the second key and the inverting input of the comparator, the non-inverting input of which is the input of the pulse-width pulse modulator, and the output is connected to the information input of the CNF, the output of which is the output of the pulse-width modulator and combined with the synchronization input of the RI, the first, second and third outputs of which are connected to the control inputs of the first key, second key and I / O, respectively, the outputs of the first and second keys are combined, and the GSI output is connected to the synchronization input of the Central Digital Clock.

 The essence of the invention is illustrated by drawings, where in FIG. 1 presents a diagram of the invention, FIG. 2 is a timing diagram of its operation, and in FIG. 3 and 4 - possible implementation options, respectively, of CNF and RI.

 The pulse-width modulator contains a GSI 1, ION 2, a comparator 3, a first key 4, an integrator 5, UVX 6, RI 7, a second key 8 and a central filter 9, and the output of the first key 4 is connected to the input of the integrator 5, the output of which is connected to the information input I / O 6, the output of ION 2 is connected to the information input of the first key 4, the output of I / O 6 is combined with the information input of the second key 8 and the inverting input of the comparator 3, the non-inverting input of which is the input of the device, and the output is connected to the information input of the CNF 9, the output of which is device output and combined with a synchronization input RI 7, the three outputs of which are connected to the control inputs of the first key 4, second key 8 and UVX 6, the outputs of the first 4 and second 8 keys are combined, and the output of the GSI 1 is connected to the synchronization input of the central filter 9.

The modulator performs a follow-up conversion of the input signal, presented in the form of a voltage, into a pulse-width signal with a constant period and a variable pulse duration. The output value is the relative pulse width of the PWM signal
θ = τ / T,
where τ is the pulse duration, and T is the pulse repetition period.

One possible embodiment of the CNF 9 is shown in FIG. 3. The CNF 9 operates in a continuous mode and reproduces the PWM sequence. As it is easy to see, the pulse period of this sequence is determined only by the frequency of the signal acting at the synchronization input of the Central Digital Phase. For the proposed CNF, it is 2 ^N periods of the clock sequence, where N is the digit capacity of the binary counter 9.5. Suppose that the stability of GSI 1, with the output of which the synchronization input of CNF 9 is connected, is quite high, therefore, for the entire considered period of time, the period of the PWM sequence is assumed to be constant and equal to some T. The pulse width of the output signal in the proposed version of CNF 9 for the current period is determined by the number stored in the binary reverse counter 9.4. Counters 9.4 and 9.5 obviously have the same bit depth. The maximum value of the pulse duration is 2 ^N periods of the synchronization signal, and the minimum is zero. At the same time, the elements And 9.2 and 9.3 block the transition of the reverse counter 9.5 from the state "2 ^N -1" to the state "0" and vice versa, which avoids failures at the borders of the range. Thus, each period of the PWM sequence, or cycle, can be associated with a specific digital equivalent N _{i of the} pulse duration, where i is the number of the cycle. This is the number of clock periods that make up the pulse width of the PWM sequence. Accordingly, the absolute and relative duration of this pulse in the ith step will be denoted as τ _i and θ _i . The clock cycle that starts at time t ₀ will be considered the first.

 The pulse distributor 7 is controlled by a signal consisting of a sequence of rectangular pulses (for example, a PWM signal), and operates according to the following algorithm.

 At the moment of the appearance of the first input pulse, a single signal appears at the first output of the RI, which goes to zero at the end of this pulse. At the second and third outputs of the RI there are zero signals.

 At the moment of arrival of the second pulse, a single signal appears at the second output and, regardless of the length of the second pulse, is held until the appearance of the third pulse. At the first and second outputs of the RI at this time, zero signals act.

 With the arrival of the third pulse, the signal at the second output is zeroed, and the signal at the third output takes a single value. At the first output, a zero signal is stored. This state, regardless of the length of the third pulse, does not change until the moment of the fourth pulse.

 The reaction of RI to the fourth control pulse coincides with the reaction to the first pulse. Further, the process is repeated cyclically in a three-stroke mode.

 Any RI implementation satisfying the above algorithm is acceptable. One possible embodiment is shown in FIG. 4.

 Pulse-width modulator operates as follows.

Let at the initial moment of time t ₀ at the input of the device acts some voltage U ₀ , constant or slowly changing. At the output of the CNF 9 there is a PWM signal characterized by a certain number N ₀ and, therefore, τ _o and θ _o . At the output of the UVC 6 there is a certain voltage U (6) ₀ . For definiteness, suppose that U ₀ > U (6) ₀ , as a result of which a positive signal takes place at the output of comparator 3.

CNF 9 responds to this signal by increasing the pulse width of the PWM sequence by one period of the clock signal, that is, in the first cycle, the pulse duration is characterized by the number N ₀ +1. In subsequent clock cycles, this process is repeated, with the only difference being that a negative signal at the output of the comparator causes a decrease in the pulse width of the output PWM signal by one elementary interval per cycle.

 RI 7, the first 4 and second 8 keys, integrator 5 and UVX 6 demodulate the output PWM signal, operating in a cyclic three-stroke mode with the time distribution of the accumulation of the reference voltage and the feedback signal, as well as sampling the voltage of the integrator 5 by means of the UVX 6 The values of the logical signals at the outputs of RI 7, the state of the first 4 and second 8 keys, as well as UVX 6 for some time intervals are given in the table.

In the first cycle, during the pulse of the PWM signal (row 1 of the table), the voltage U _op from ION 2 through the first switch 4, closed by a single control signal from output 1 of RI 7, passes to the input of the integrator 5, which accumulates this voltage and generates the output signal U (5) ₁ .

At the moment of the end of the pulse of the PWM signal t ' ₀ (row 2 of the table) RI 7 generates at the output 1 a zero control signal that opens the first switch 4. The voltage U _op ceases to pass to the input of the integrator 5, which goes into the information storage mode. The output of the integrator 5 continues to operate voltage U (5) ₁ .

In the second clock cycle (row 3 of the table), with the arrival of a pulse of the PWM signal, a single signal appears at the output 2 of RI 7. This causes the second key 8 to close, as a result of which the voltage U (6) ₀ from the output of the UVX 6 is supplied to the input of the integrator 5 and generates a voltage at its output equal to a certain value of U (5) ₂ .

In the third clock cycle (row 4 of the table), with the arrival of a pulse of the PWM signal, the output 2 of the RI 7 is reset, and the output 3 of the RI 7 produces a single signal, which leads to the opening of the second key 8 and to switch the UVX 6 to the sample mode. At the output of the UVX 6, the voltage U (6) ₁ is set equal to U (5) ₂ .

 In the next cycle, outputs 1, 2, and 3 of RI 7 will set logic signals 1, 0, and 0, respectively, and a single signal at the first output of RI 7 will go to zero at the end of the pulse of the output PWM signal, which will correspond to rows 1 and 2 of the table . The stages of the demodulation process will thus be further cyclically repeated, and the duration of this cycle will be three cycles.

а n - номер такта работы устройства. В конце каждого трехтактного цикла напряжение на выходе УВХ 6 устанавливается равным напряжению на выходе интегратора 5 в конце второго такта этого цикла. Это напряжение будет равно

где τ - постоянная времени интегратора 5;
τ_k - длительность импульса ШИМ-сигнала в первом такте k-го цикла;
U(6)_k-1 - напряжение на выходе УВХ 6 в предыдущем, (k-1)-м цикле.To denote the numbers of three-stroke cycles, we apply the index k, where

and n is the number of the clock cycle of the device. At the end of each three-stroke cycle, the voltage at the output of the UVX 6 is set equal to the voltage at the output of the integrator 5 at the end of the second cycle of this cycle. This voltage will be equal

where τ is the time constant of integrator 5;
τ _k - pulse width of the PWM signal in the first cycle of the k-th cycle;
U (6) _k-1 is the voltage at the output of the UVX 6 in the previous, (k-1) th cycle.

Для установившегося режима, когда τ_k= τ_k-1, где τ_k-1 - длительность импульса в цикле, предшествующем рассматриваемому, U(6)_k-1 = U(6)_k. Тогда выражение (2) примет следующий вид:

откуда

или

что равносильно
U(6)_k = θH, (4)
где коэффициент обратной связи H = -U_оп, a θ - относительная длительность выходного ШИМ-сигнала устройства.Since U (6) _k-1 and U _op are obviously constants for cycle k, expression (1) can be transformed:

For the steady state, when τ _k = τ _k-1 , where τ _k-1 is the pulse duration in the cycle preceding the considered one, U (6) _k-1 = U (6) _k . Then expression (2) will take the following form:

where from

or

which is equivalent
U (6) _k = θH, (4)
where the feedback coefficient H = -U _op , and θ is the relative duration of the output PWM signal of the device.

Отметим, что второй ключ 8 замыкает цепь обратной связи интегратора 5 на время, равное длительности одного такта. Следовательно, время выборки УВХ 6 может также достигать величины периода ШИМ-сигнала t_выб=Т.As follows from expression (1), the voltage at the output of the UVX 6 at the end of an arbitrary cycle k depends only on two quantities that change during operation: the pulse width of the PWM signal in the first cycle of this cycle τ _k and the voltage at the output of the UVX 6 at the end of the previous cycle U (6) _k-1 . Thus, when the pulse width of the PWM signal in the first cycle of the (k + 1) th cycle changes by Δτ, the process will switch to the steady state at the end of this cycle, i.e. after three clock cycles:

Note that the second key 8 closes the feedback circuit of the integrator 5 for a time equal to the duration of one cycle. Therefore, the sampling time of the UVX 6 can also reach the value of the period of the PWM signal t _select = T.

где S есть величина зоны нечувствительности компаратора 3 по напряжению.Thus, a voltage directly proportional to θ is generated at the inverting input of the comparator 3 using ION 2, the first 4 and second 8 keys, an integrator 5, UVX 6 and RI 7. At the same time, from the operation logic of the CNF 9, the value of θ is determined the relation θ _n = θ _n-1 + Δθ _n , and

where S is the value of the dead zone of the comparator 3 voltage.

причем U_оп должно быть противоположно U по знаку.The last condition begins to be satisfied at some point in time t _r (see Fig. 2), when the difference between the voltages at the input of the comparator 3 enters the deadband of the comparator and the output value ceases to increase. In this case, the pulse width of the output PWM signal is characterized by the number N _r and has a relative duration θ _r .
In the steady state, Δθ _n = 0, i.e., the difference between the initial and reconstructed voltages from the output signal is less than the value of the dead band of the comparator, i.e., U≈U can be considered (6). From here and from (4) follows the expression for the transfer function of the modulator:

and U _op must be opposite to U in sign.

 It can be seen from expressions (3) and (4) that the transmission coefficient of the modulator in principle does not depend on the value of the integrator time constant τ. Thus, it is shown that the inherent error of the prototype caused by deviations of the real values of the integrator time constants from each other and from the period of the PWM signal is absent in the claimed device, which means that the accuracy of converting the input voltage to the relative pulse width of the PWM signal is increased.

 In addition to the marked increase in accuracy, the device has better adaptability. According to the foregoing, practically only digital components are introduced into the structure of a pulse-width modulator, and integrators are excluded, which require the use of precision resistors and capacitors, as well as an adder and multiplier, also containing resistors. At present, digital components are much more affordable and more practical than precision analogue ones, since they are relatively cheaper, more technologically advanced in integrated design and have significantly better overall dimensions compared to discrete precision and superprecision elements. This simplifies the pulse-width modulator compared to the prototype, increases the reliability of the device, reduces its cost.

Sources of information
1. Smolov VB, Ugryumov EP, Artamonov A.B. et al. Time-pulse computing devices. / Ed. V.B. Smolova, E.P. Ugryumova. - M .: Radio and communications, 1983.

 2. Count R. Electronic circuits: 1300 examples: Per. from English - M.: Mir, 1989.

3. A. S. USSR N 1619391, MKI ⁵ H 03 K 7/08, publ. 01/07/1991. Bull. N 1 (prototype).

Claims (1)

 A pulse-width modulator comprising a clock pulse generator, a reference voltage source, a comparator, a first key, an integrator, a sample-storage device, the output of the first key being connected to an integrator input, the output of which is connected to an information input of the sample-storage device, characterized in that an impulse distributor, a second switch and a digital accumulating driver of a pulse-width modulated (PWM) signal are additionally introduced into it, and the output of the reference voltage source is connected nen with the information input of the first key, the output of the sample-storage device is combined with the information input of the second key and the inverting input of the comparator, the non-inverting input of which is the input of the pulse-width modulator, and the output is connected to the information input of the digital accumulating driver of the PWM signal, the output of which is the output pulse-width modulator and combined with the synchronization input of the pulse distributor, the first, second and third outputs of which are connected to the control inputs respectively of the first key, the second key, and the sample-storage device, the outputs of the first and second keys are combined, and the output of the synchronizing pulse generator is connected to the synchronization input of the digital accumulating driver of the PWM signal.

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