RU2159506C1 - Code-analog converter - Google Patents

Abstract

FIELD: automatic control equipment. SUBSTANCE: device has pulse-width modulation signal source, reference voltage source, gates, inverting integrator, memory unit, AND gate, counter and decoder. EFFECT: increased precision. 2 dwg, 1 tbl

Description

 The present invention relates to electrical circuits of digital-to-analog converters and can be used in the construction of digital measuring devices and analog-to-digital computing devices.

 There is a simple and fairly accurate converter using a device for sampling-storing (UVX) information [1, Fig. 40]. It consists of a source of the converted code signal, presented in a width-modulated (PWM) form, a voltage reference source, a key, a two-input integrator, and a UVX. However, the disadvantage of this converter is its low speed, since the repetition period of the PWM signal cannot be less than milliseconds - hundreds of microseconds due to the need for sampling with a short pulse, the duration of which should be much less than the repetition period of the PWM signal.

 Of the analogues, the closest in technical essence is the code-to-analog converter [2], which is chosen as a prototype. The prototype has a significantly higher speed compared to the device [1] due to the fact that there is no need to generate a short gate pulse for recording information in the I / O.

 The prototype includes a PWM signal source, a reference voltage source (ION), the first and second switches, an inverting integrator, a sampling-storage device (I / O), an “I” element, a counter and a feedback resistor, and an integrator input consisting of a resistor , a capacitor and an operational amplifier, is the first output of the resistor, the second output of which is combined with the first output of the capacitor and with the inverting input of the operational amplifier, the non-inverting input of which is connected to a common point, and the output is connected to the second output to the capacitor and is the integrator’s output, the ION output is connected to the information input of the second key, connected at the output to the integrator’s input, the output of which is connected to the information input of the I – V circuit, the output of which is the device output and connected to the information input of the first key, and the PWM signal source output is connected with the counting input of the counter and with the first input of the "And" element, the output of which is connected to the control input of the second key, the feedback resistor is connected by its first output to the output of the first key, and the second to vodom to the inverting input of the operational amplifier of the integrator, the output line counter is connected to a control input of the first switch and to a second input of the "AND" and the inverse output - the counter is connected to the control input of the SHA.

The prototype performs push-pull conversion of the relative pulse width of the input PWM signal τ _and / T into a voltage proportional to it. Here, τ _and is the pulse duration, and T is the period of the PWM signal.

 The disadvantage of the prototype is the low accuracy, as the conversion result includes an error due to differences in the actual values of the resistances of the integrator resistor and feedback resistor.

 The technical result of the proposed invention is to improve the accuracy of the Converter.

 The objective of the proposed invention is the creation of a code-to-analog converter with a single integration path, which eliminates the error caused by the non-identity of the resistors.

 The problem is solved by creating a device containing a PWM signal source, a reference voltage source, first and second keys, an inverting integrator, a sample-storage device, an "I" element, a counter, and the input of an integrator consisting of a resistor, capacitor and operational amplifier is the first output of the resistor, the second output of which is combined with the first output of the capacitor and with the inverting input of the operational amplifier, the non-inverting input of which is connected to a common point, and the output is connected to the second the capacitor’s water and is the output of the integrator, the output of the reference voltage source is connected to the information input of the second key, connected at the output to the integrator input, the output of which is connected to the information input of the sample-storage device, the output of which is the output of the device and connected to the information input of the first key, and the output of the PWM signal source is connected to the counting input of the counter and to the first input of the AND element, the output of which is connected to the control input of the second key. A feedback resistor is excluded from the inventive device and a decoder is introduced, the first and second direct outputs of the counter are connected respectively to the first and second inputs of the decoder, the zero, first, second and third outputs of which are connected respectively to the second input of the "And" element, the control input of the first key , the control input of the sample-storage device and the counter reset input, and the output of the first key is connected to the integrator input.

 The essence of the alleged invention is illustrated by drawings, where in FIG. 1 is a diagram of the alleged invention, and FIG. 2 - time diagrams of his work.

 The converter contains a PWM signal source 1, a reference voltage source (ION) 2, the first 3 and second 4 keys, an inverting integrator 5, a sampling-storage device (I / O) 6, an I element 7, a counter 8 and a decoder 9, with an input the integrator 5, consisting of a resistor 10, a capacitor 11 and an operational amplifier 12, is the first output of the resistor 10, the second output of which is combined with the first output of the capacitor 11 and the inverting input of the operational amplifier 12, the non-inverting input of which is connected to a common point, and the output is connected to second in the water of the capacitor 11 and is the output of the integrator, the output of the ION 2 is connected to the information input of the second key 4, connected at the output to the input of the integrator 5, the output of which is connected to the information input of the UVX 6, the output of which is the output of the device and connected to the information input of the first key 3, and the output of the source of the PWM signal 1 is connected to the counting input of the counter 8 and to the first input of the element "I" 7, the output of which is connected to the control input of the second key 4, the first and second direct outputs of the counter 8 are connected respectively to the first and second inputs of the decoder 9, the zero, first, second and third outputs of which are connected respectively to the second input of the element "And" 7, the control input of the first key 3, the control input of the I / O 6 and the reset input of the counter 8, and the output of the first key 3 is connected to integrator input 5.

 At the output of the PWM signal source 1, a periodic pulse signal with a period of T. is active. The time between the moments of the start of adjacent pulses is called the beat. The clock cycle that starts at time to will be considered the first.

 The converter performs a three-stroke conversion of the relative pulse width of the PWM signal to voltage with the time distribution of the accumulation of the input signal and the feedback signal, as well as the sampling of the integrator voltage by the sampling-storage device. The values of the logical signals at the outputs of the counter 8 and the decoder 9, the state of the first 3 and second 4 keys, as well as UVX 6 for various time intervals of one cycle are given in table. 1.

 The converter operates as follows.

Suppose that at the initial moment of time t _{0 the} counter 8 contains the value "0", which corresponds to the first row of the table. 1. At the output of the integrator 5 acts some initial voltage U _and ⁰ . The first key 3 is open, and the UVX 6 is in storage mode, controlled by zero signals from the first and second outputs of the decoder 9, respectively. At the output of the UVX 6 there is a certain voltage U ₀ .

In the first cycle, during the pulse of the PWM signal (line 1, table. 1), the voltage U _op from ION 2 through the second switch 4, closed by a control signal from the output of the element "And" 7, passes to the input of the integrator 5, which accumulates this voltage and generates an output signal U _and ¹ .

At the moment of the end of the pulse of the PWM signal t ' ₀ (line 2, table 1), the element "AND" 7 generates a zero control signal that opens the second switch 4. The voltage U _op ceases to pass to the input of the integrator 5, which goes into the information storage mode. The output of the integrator 5 acts some voltage U _and ¹ .

In the second clock cycle (line 3, Table 1), with the arrival of the pulse of the PWM signal, counter 8 goes into state 1, the first key 3 is closed by a single signal from the first output of the decoder 9, and the second key 4 remains open, resulting in a voltage of U ₀ from the output of the I – V circuit, it goes to the input of the integrator 5 and generates a voltage at its output equal to a certain value of U _and ² .

In the third step (line 4, Table 1), with the arrival of a pulse of the PWM signal, counter 8 goes into state 2, the first key 3 is opened with a zero signal from the first output of the decoder 9, and the second key 4 remains open. UVX 6, controlled by a single signal from the second output of the decoder 9, goes into sampling mode. At the output of the UVX 6 (i.e., at the output of the device), the voltage U ₁ is set equal to U _and ² .

In the next clock cycle (line 5, Table 1), with the arrival of the pulse of the PWM signal, the counter 8 goes to state 3. After a short delay time t _ass , introduced by the decoder 9, it is reset to the initial state 0 (line 1, table 1 ) under the influence of the positive edge of the control signal from the third output of the decoder 9. Obviously, this cycle of the device will proceed similarly to the first cycle, and, therefore, the process will be cyclically repeated.

In the future, each of the three consecutive clock cycles of the converter will be similar to the first, second, and third clocks, respectively. This sequence of measures will be called a cycle. The pulse width at the output of the PWM signal source 1 in the first clock cycle of the nth cycle will be denoted by τ _n , and in the second and third clock cycles the pulse width does not matter, since it does not affect the operation of the converter. The voltage at the output of the device at the end of the nth cycle is denoted by U _n .

(1)
где τ = RC - постоянная времени интегратора 5, определяемая значениями сопротивления R резистора 10 и емкости С конденсатора 11, входящих в состав интегратора 5;
U_n-1 - напряжение на выходе устройства в предыдущем, (n-1)-м цикле.As already noted, the voltage at the output of the device at the end of each cycle is set equal to the voltage at the output of the integrator 5 at the end of the second cycle of this cycle. At the output of the integrator at the end of the second clock cycle of the nth cycle (and therefore at the output of the device at the end of this cycle) we will have:

(1)
where τ = RC is the time constant of the integrator 5, determined by the resistance values R of the resistor 10 and the capacitance C of the capacitor 11, which are part of the integrator 5;
U _n-1 - voltage at the output of the device in the previous, (n-1) -th cycle.

Для установившегося режима, когда τ_n= τ_n-1, где τ_n-1 - длительность импульса в цикле, предшествующем рассматриваемому, U_n-1 = U_n. Тогда выражение (2) примет следующий вид:

где коэффициент передачи устройства К = -U_оп.Since U _n-1 and U _op are obviously constants for cycle n, expression (1) can be converted:

For the steady state, when τ _n = τ _n-1 , where τ _n-1 is the pulse duration in the cycle preceding the considered one, U _n-1 = U _n . Then expression (2) will take the following form:

where the transmission coefficient of the device K = -U _op .

Отметим, что первый ключ 3 замыкает цепь обратной связи интегратора 5 на время, равное длительности одного такта. Следовательно, время выборки УВХ 6 может также достигать величины периода ШИМ-сигнала Т_выб, как у прототипа.As follows from expression (1), the voltage at the output of the device at the end of an arbitrary cycle n depends only on two quantities that change during operation: the pulse width of the PWM signal in the first cycle of this cycle τ _n and the voltage at the output of the device at the end of the previous cycle U _n-1 . Thus, when the pulse width of the PWM signal in the first cycle of the (n + 1) -th cycle changes by the value of Δτ, the process switches to the steady state at the end of this cycle, i.e. after three clock cycles:

Note that the first key 3 closes the feedback circuit of the integrator 5 for a time equal to the duration of one cycle. Therefore, the sampling time of the UVX 6 can also reach the value of the period of the PWM signal T _select , as in the prototype.

 From the expressions (3) and (4) it can be seen that the transmission coefficient of the device in principle does not depend on the value of the integrator time constant τ. Thus, it is shown that the inherent error of the prototype, caused by the non-identity of the resistors in the input circuits of the integrator, is absent in the claimed device, which means that the accuracy of converting the relative pulse width of the PWM signal to the output voltage is increased.

 In addition to the marked increase in accuracy, the device has better adaptability. According to the above, one digital element, a decoder, is introduced into the structure of the code-to-analog converter. One analog element is also excluded from it, to which stringent requirements for accuracy are imposed, namely a resistor. At present, digital components are much more affordable and more practical than precision analog ones, since they are relatively cheaper, more technologically advanced in integrated design and have significantly better mass and dimensional parameters compared to discrete precision and super-precision elements. Thereby, simplification of the code-to-analog converter is achieved in comparison with the prototype, the reliability of the device is increased, and its cost is reduced.

SOURCES OF INFORMATION
1. Gutnikov BC The use of operational amplifiers in measurement technology. -L.: Energy, 1983.

2. A.S. 1508347 USSR, IPC ⁶ H 03 M 1/66. Code-to-analog converter / N.M. Safyannikov, V.B. Smolov, E.P. Ugryumov, A.P. Pototsky (RF). - Publ. 03/20/99, Bull. N8, 1999 (prototype).

Claims (1)

 A code-analog converter containing a source of a width-modulated signal, a reference voltage source, first and second keys, an inverting integrator, a sampling-storage device, an And element, and a counter, and the input of an integrator consisting of a resistor, a capacitor, and an operational amplifier, is the first output of the resistor , the second output of which is combined with the first output of the capacitor and with the inverting input of the operational amplifier, the non-inverting input of which is connected to a common point, and the output is connected to the second output of the con of the sensor and is the integrator’s output, the output of the reference voltage source is connected to the information input of the second key, connected at the output to the integrator’s input, the output of which is connected to the information input of the sample-storage device, the output of which is the device’s output and connected to the information input of the first key, and the output the source of the pulse-width modulated signal is connected to the counting input of the counter and to the first input of the element And, the output of which is connected to the control input of the second key, characterized in that about, a decoder is introduced into it, and the first and second direct outputs of the counter are connected respectively to the first and second inputs of the decoder, the zero, first, second and third outputs of which are connected respectively to the second input of the And element, the control input of the first key, the control input of the sample-storage device and the counter reset input, and the output of the first key is connected to the integrator input.

Images