SU828101A1 - Power factor to code converter - Google Patents

Description

The invention relates to electrical engineering and can be used for digital measurement of power factor.

A known power factor to DC to DC converter comprising a reference voltage source, a differential amplifier, low-pass filters, an adjustable amplifier, a controlled rectifier, switches, a switching frequency generator and a limiter amplifier [1].

The disadvantages of the converter are low speed due to the presence of low frequency filters in the circuit - 15,000.

The closest solution in technical essence is a power factor converter to a code containing a switch, the output of which is connected via an amplifier-limiter in a time interval, the reference voltage generator, the output of which is connected through a divider and one of the keys to 25 version counter, and through the second key connected to the code to frequency converter, the output of the divider through the third key connected to the counter [2].

Such a pseobrazovatel possesses low 30 reliability and speed, since its conversion cycle consists of three clock cycles.

The aim of the invention is to increase the speed and reliability of the Converter.

This goal is achieved in that the Converter, containing the first amplifier-limiter, integrating the voltage Converter in the time interval (IPNV), the reference frequency generator, the output of which is connected to the first input of the key, the counter and the control unit, and the output of the key is connected to the input of the counter, a second limiting amplifier and two integrating samplers, the first input bus being connected through the first integrating sampler to the first input of the integrating voltage converter in the time interval through the second sampler with its second input, through the first amplifier-limiter with the clock input of the second integrating sampler and with the first input of the control unit, the second input of which is connected to the clock input of the first integrating sampler and through the second amplifier the limiter with the second input bus . The output of the control unit is connected respectively to the control inputs of the first, second integrating discretizers and an integrating voltage converter in a time interval, the output of which is connected to the second key input.

The structural diagram of the proposed Converter is shown in the drawing.

The inputs of the integrating transducer are connected to the outputs of the integrating discretizers 2, 3, and the output of the transducer is connected via a key 4 to the counter input

5. The second input of the key 4 is connected to the output of the reference frequency generator 6, the first input bus of the device is connected to the input of the amplifier-limiter 7 and the signal inputs of the samplers 2,3. The second input bus of the device is connected to the input of the second amplifier-limiter 8, the output of which is connected to the clock input of the sampler 2 and the input of the control unit 9. The output of the amplifier-limiter 8 is connected to the clock input of the integrating sampler 3 and the input of the control unit 9. The outputs of the latter are simultaneously connected to control inputs of discretizers 3 and integrating transducer 1.

The converter operates as follows.

Let the voltage U _u (t) = (J _m sin (ωί + φ) be applied to the input of amplifier 8, and the voltage (ί) - U _M sin ω / connected to the inputs of amplifier 7 and integrating discretizers 2 and 3.

The integrating discretizer is an integrator with impulse feedback and a conversion function and - and EXIT - input _D 1 where U _BX is the average value of the input voltage over the integration interval T _to ;

Ri and T? 2 are the resistances of the resistors included in the circuit of integrating discretizers.

In the converter, the integration cycle of each sampler 2 or 3 is set by the corresponding limiting amplifier 7 or 8 and is equal to the half-cycle of its input voltage. On command from the control unit 9, the input voltage Ui (t) = U _m sinwt is simultaneously integrated by sampler 2 during the half-cycle of the signal U _u (t) = U _m sin (ωί + φ) and sampler 3 is of the same voltage, but in the half-cycle of the voltage U ^ t) = U _m sin ωί. As a result, at the output of the first sampler we get the voltage and _r = cos φ, (1) and at the output of the second - and, = K ₂ and ^ (2) where t / _C p is the average value of the input signal;

Κι and К ₂ - conversion coefficients of discretizers 2 and 3.

After the clock cycle of the discretizers is completed, at the command from the control unit 9, the output voltages Ut and U _{2 are} converted to an interval in the converter 1, the conversion function of which has the form where Aipnv is the IPRF conversion coefficient;

L / ι and U ₂ - input voltage IPNV; T _about - a fixed time interval specified from the control unit 9.

Substituting in (3) the values of the stresses Ζ7ι (1) and t / ₂ (2), we obtain

T _x - D'-COS φ, where # = - £ - / < _И п _HB (4)

Λ 2 is the total conversion coefficient.

The output time interval IPNV 1 is measured by the pulse-counting method, by filling the counter 5 through the public key 4 pulses from the reference frequency generator 6 with a frequency Fa. As a result, in counter 5 we get the code

N = cos ©. (5)

The entire conversion cycle of the device consists of two clock cycles - the clock cycle of the integrating discretizers 2 and 3 and the clock cycle of the integrating converter 1.

In addition, it should be noted that in the device, the conversion cycle consists of two clock cycles only during the first measurement, while re-measurement, the cycle consists of one clock cycle of the IPRN, since the output signals of discretizers 2 and 3 take steady values defined by expressions (1) and ( 2).

Claims (2)

1.Ornatsky P.P. et al. Measuring instruments for periodic comparison, M., “Energy, 1975. 2. USSR author's certificate number 659973, cl. G01 R21/00, 1979 (prototype).