RU2240569C1 - Integral transformer - Google Patents

Abstract

FIELD: electronics.

SUBSTANCE: device has integrator, two comparators, three biased multi-vibrators, counters, encoder, logical elements, commutator and impulses generator. Operation of transformer is based on integration of input signal and flushing generator indications when output signal reaches integrator of given level. Impulses generator, counters, encoder, one of multi-vibrators, commutator and logical elements form a circuit for compensating signal of transformer displacement or current sensor.

EFFECT: higher efficiency.

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Description

The invention relates to the field of electronic technology and can be used to convert current to frequency in devices with high requirements for reliability and accuracy of conversion.

A known voltage-to-frequency converter, see, for example, described in [1], containing a series-connected integrator, a first comparator, a first one-shot, covered by negative feedback to the first input of the integrator, a second input of the integrator is connected to the input of the integral converter, and the output of the first one-shot with the first input of the switch.

A disadvantage of the known device is that it does not allow compensation of the zero signal (bias signal) of both the converter itself and the bias signal of the current sensor, which in many cases does not allow to obtain the required conversion accuracy.

The closest technical solution to the proposed one is an integrated converter [2], containing an integrator, first and second comparators, first and second one-shots, a switch, a reversible counter, a code-voltage converter.

The disadvantage of this device is that it has a large transient time during which the required compensation accuracy (bias signal) of both the converter itself and the bias signal of the current sensor is achieved.

The objective of the invention is to reduce the transient time, during which the required accuracy of compensation (bias signal) is achieved for both the converter itself and the bias signal of the current sensor.

This task is achieved by the fact that into an integrated converter comprising, an integrator, first and second comparators, first and second single vibrators, a switch and a reversible counter, the summing and subtracting inputs of which are connected to the corresponding outputs of the switch, the control input of which is connected to the control signal bus, and the input the integral converter is connected to the input of the integrator, the output of which is connected to the inputs of the first and second comparators, connected by their outputs to the inputs of the first and second of one-vibrators, the outputs of which are connected respectively to the inverting and non-inverting inputs of the integrator, the first and second OR elements, the first, second, third and fourth AND elements, a pulse generator, a pulse counter, a third one-shot, an encoder and a programmable counter, whose control inputs are additionally introduced connected to the corresponding outputs of the encoder, the C-input of the programmable counter is connected to the output of the fourth element And, the first input of which is connected to the non-inverse output of the pulse counter, and the second input is connected to the output of the pulse generator and the first input of the third AND element, the second input of which is connected to the control signal bus, and the third input is connected to the inverse output of the pulse counter, the C-encoder outputs are connected to the corresponding outputs of the reversible counter, whose non-inverse sign discharge output is connected with the first input of the first element And, and the inverse output of the sign discharge is connected to the first input of the second element And, the output of the programmable counter is connected to the output of the third one-shot, in the course of which is connected to the second inputs of the first and second elements AND, connected by their outputs respectively to the second inputs of the first and second elements OR, the first inputs of which are connected respectively to the outputs of the first and second single vibrators, and the outputs of the first and second elements OR are connected to the corresponding inputs of the switch and are the outputs of the integrated converter.

The drawing shows a block diagram of an integrated converter, where 1 is an integrator, 2 is a first comparator, 3 is a first one-shot, 4 is a second comparator, 5 is a second one-shot, 6 is a first OR element, 7 is a second OR element, 8 is a first element And, 9 - the second element And, 10 - the switch, 11 - the reverse counter, 12 - the input of the integrated Converter, 13 - the bus of the control signal, 14 - the pulse generator, 15 - the third element And, 16 - the pulse counter, 17 - the fourth element And , 18 - programmable counter, 19 - third one-shot, 20 - encoder.

In the integrated converter, the output of the integrator 1 is connected to the inputs of the first 2 and second 4 comparators, the outputs of which are connected respectively to the inputs of the first 3 and second 5 single-vibrators. The output of the first one-shot 3 is connected to the inverting input of the integrator 1 and the first input of the first element OR 6, the second input of which is connected to the output of the first element And 8. The output of the second one-shot 5 is connected to the non-inverting input of the integrator 1 and the first input of the second element OR 7, the second input of which connected to the output of the second element And 9. The output of the pulse generator 14 is connected to the first input of the third element And 15 and the second input of the fourth element And 17, the first input of which is connected to the non-inverse output of the pulse counter 16, the inverse output of which is connected to the third input of the third element And 15. The control signal bus 13 is connected to the second input of the third element And 15 and the control input of the switch 10, the outputs of which are connected to the corresponding inputs of the reversing counter 11, the output signals of which are connected to the corresponding inputs of the encoder 20. The non-inverse sign output of the reversible counter 11 is connected to the first input of the first element And, the inverse sign output is connected to the first input of the second element And 9. The output is four of the second element And 17 is connected to the C-input of the programmable counter 18, the output of which is connected to the input of the third one-shot 19, and the control inputs of the programmable counter 18 are connected to the corresponding outputs of the encoder 20. The output of the one-shot 19 is connected to the second inputs of the first 8 and second 9 elements I. The outputs of the first 6 and second 7 elements OR are connected to the corresponding inputs of the switch 10 and are the outputs of the integrated Converter. The output of the third element And 15 is connected to the C-input of the pulse counter 16, the input of the integral Converter 12 is connected to the input of the integrator 1.

The converter operates as follows. The current supplied to input 12, enters the input of the integrator 1, causing an increase in voltage at its output. Upon reaching the threshold level of the first 2 (or second 4) comparator, the last one is triggered and a high level will appear at its output, which will go to the input of the first 3 (or second 5) one-shot. As a result of this, the one-shot will generate a pulse of a strictly defined duration and amplitude. This pulse will arrive at the inverting (or non-inverting) input of the integrator 1 and will reduce the voltage level at the output of the latter. At the same time, this pulse will arrive at one of the outputs of the integrated converter, passing through the first 6 (or second 7) OR element.

If it is necessary to compensate for the bias signal (varying from temperature, from on to on, etc.) of both the converter itself and the current sensor, it is necessary to apply an enable level to the control signal bus 13. This level will go to the control input of the switch 10 and allow the passage of pulses from the output of the first 6 and second 7 OR elements to the summing or subtracting inputs of the reverse counter 11. In the initial state, the pulse counter 16 is reset and its output signal U _n at the non-inverting output is low ( U _n = 0), and at the inverting output a high level (U _and = 1). In this case, the signals from the output of the pulse generator 14 do not pass to the C-input of the programmable counter 18, since the fourth element And 17 blocks their passage. At the same time, the signals from the output of the pulse generator 14 through the third element And 15 are fed to the C-input of the pulse counter 16. When the last discharge of the pulse counter 16 is in the single state (output signals U _n = 1, U _and = 0), the third element And 15 blocks the passage signals from the output of the pulse generator 14 to the C-input of the pulse counter 16, and the fourth element And 17 allows the passage of these signals to the C-input of the programmed pulse counter 18.

Let the pulse counter 16 and the reverse counter 11 have (n + 1) discharge, the programmable counter 18 has n bits, and the frequency of the pulse generator 14 is f ₀ . The time T ₀ from the moment the control signal arrives on bus 13 until the signal U _n = 1 appears will be 2 ⁿ / f ₀ . During this time, pulses from the output of the integral converter f ₊ will correspond to the input of the reversible counter 11, corresponding, for example, to a positive bias signal. Let during the time T ₀ to the input of the reverse counter 11 received N pulses. For the complete compensation of the bias signal, it is necessary to form N pulses corresponding to the negative input signal at the output of the integrated converter during each time interval To.

Let the bias signal be such that the frequency of the output signal of the integrated converter is f _cm . During the time T _{0 the} number of pulses N = f _cm · T ₀ will arrive at the input of the reversible counter. If the maximum value of f _cm corresponding to the maximum possible bias signal is f _cm.max , then during the time T _{0, the} number of pulses N _max = f _{cm max} · T ₀ will arrive at the input of the reverse counter 11. Choose T ₀ such that N _max = 2 ⁿ -1. In this case, the frequency f _{0 of} the pulse generator 14 is set as

If during the time T ₀ at the input of the reverse counter 11 receives N pulses, then the frequency f _cm will be equal to

Let us consider in more detail the operation of the integrated converter. After the time T _{0 has} elapsed, an encoder 20 is generated at the input of the encoder 20. The encoder 20 generates a code at its output such that the division coefficient K _{d of the} programmable counter 18 when pulses of frequency f ₀ arrive at its input ensures the pulse repetition rate f _see In accordance with (1) and (2), the division coefficient K _d is determined as

At time T _0, pulses of frequency f ₀ begin to arrive at the input of programmable counter 18. At the output of the programmable counter 18, pulses with a frequency of f _cm are generated, which are converted to a predetermined duration by a single-shot 19. Since a positive number N is recorded in the reverse counter 11, the output signal at the non-inverting output of the sign discharge of the reverse counter 11 U ₊ = 0 (low level), and at the inverting output U _- = 1 (high level). In this case, the signal U _- = 1 allows the passage of pulses from the output of the third one-shot 19 through the second element And 9 to the input of the second element OR 7, from the output of which pulses are generated f _- at the second output of the integral Converter. Thus, the output signal of the integrated transducer, defined as the algebraic sum of the pulses f ₊ and f _- for a certain period of time, will be close to zero. In other words, from the moment of time T _{0 the} integrated converter provides full compensation of the bias signal.

In the case of a negative bias signal, N pulses will arrive at the subtracting input of the reverse counter 11 during the time T ₀ and the code of this counter corresponds to a negative number. In this case, the output signal at the non-inverse output of the sign discharge of the reversible counter 11 U ₊ = 1 (high level), and at the inverse output U _- = 0 (low level). The signal U ₊ = 1 allows the passage of pulses from the output of the third one-shot 19 through the first element And 8 to the input of the first element OR 6, from the output of which the pulses f ₊ integral Converter The encoder 20 converts the module of the number N into a code, providing a division ratio of the programmable counter in accordance with (2). As in the case of positive displacement transducer output signal integral, defined as the algebraic sum of the pulse f ₊ and f _- for a certain period of time will be close to zero.

Compared with the known integrated converter [2], the proposed solution provides a significantly shorter transition time. Suppose that the input signal varies within ± 10 mA, and the bias signal is I _cm.max = ± 0.1 mA. We also assume that the integrated converter must compensate for the bias signal to the level Δ = 0.0001 mA. In the known device, in the process of compensating for the bias signal, each pulse received at the input of the reversible counter changes the input signal by Δ. Determine the transient time T _p in the known device when performing signal compensation I _cm.max . Given that the ratio I _cm.max / Δ = 1000, the number of digits of the reverse counter is n = 10. Let an input signal of 10 mA correspond to an output signal frequency of 1000 Hz. In this case, with the input signal Δ = 0.0001 mA, the frequency of the output signal will be O, 01 Hz, which corresponds to the pulse repetition period TΔ = 100 s. The transition time TΔ in the known device can be determined in the form

This time T _p ≅ 650 s. When carrying out compensation, each pulse at the output of the integrated converter entering the input of the reversible counter reduces the signal at the input of the integrator by Δ, which reduces the time that the output signal of the integrator 1 reaches the comparator threshold, which reflects equality (4).

In the proposed solution, we choose T ₀ = TΔ. This time determines the time of the transition process T _p = 100 from the proposed Converter, which directly follows from the description. Thus, the transition time of the proposed integrated Converter is several times less than the transition time of the known device. Reducing the transition time of the offset signal compensation process is essential, for example, when using an integrated converter in dynamic systems, for example, in spacecraft motion control systems in accelerometer signal conversion channels, where the compensation time (shutdown time of executive engines) is very limited.

The proposed set of features in the solutions considered by the authors was not found to solve the problem and does not follow explicitly from the prior art, which allows us to conclude that the technical solution meets the criteria of "novelty" and "inventive step". As elements for the implementation of the device, you can use standard circuits of the integrator, comparator, one-shot and logic elements of digital circuits of any series, for example, 564, etc.

Literature

1. USSR author's certificate N 921080, cl. H 03 K 13/20, dated July 24, 81. Voltage to frequency converter.

2. Patent of the Russian Federation N 2138826, IPC 6 G 01 R 19/252 from 27. 09. 99. Integrated converter.

Claims (1)

An integrated converter comprising an integrator, first and second comparators, a first and second single vibrator, a switch and a reversible counter, the summing and subtracting inputs of which are connected to the corresponding outputs of the switch, the control input of which is connected to the control signal bus, and the input of the integral converter is connected to the integrator input, the output of which is connected to the inputs of the first and second comparators, connected by their outputs, respectively, to the inputs of the first and second one-shots, the outputs of which x are connected respectively to the inverting and non-inverting inputs of the integrator, characterized in that the first and second elements OR, the first, second, third and fourth elements AND, the pulse generator, pulse counter, third one-shot, encoder and programmable counter, inputs are additionally introduced into it the control of which is connected to the corresponding outputs of the encoder, the C-input of the programmable counter is connected to the output of the fourth element And, the first input of which is connected to the non-inverse output of the pulse counter, and the second the input is connected to the output of the pulse generator and the first input of the third AND element, the second input of which is connected to the control signal bus, and the third input is connected to the inverse output of the pulse counter, the C-input of which is connected to the output of the third AND element, while the inputs of the encoder are connected to the corresponding outputs of the reversible counter, the non-inverse output of the sign discharge is connected to the first input of the first element And, and the inverse output of the sign discharge is connected to the first input of the second element And, the output is programmable the second counter is connected to the output of the third one-shot, the output of which is connected to the second inputs of the first and second elements AND, connected by their outputs respectively to the second inputs of the first and second elements OR, the first inputs of which are connected respectively to the outputs of the first and second one-shots, and the outputs of the first and second OR elements are connected to the corresponding inputs of the switch and are the outputs of the integrated converter.