RU2145149C1 - Sigma-delta analog-to-digital converter - Google Patents

Abstract

FIELD: special-purpose electronic engineering. SUBSTANCE: real-time inverting analog-to-digital converter of sigma-delta architecture has series-connected adder, integrator, clock comparator, and digital filter; it also has one-bit digital-to-analog converter and polarity-reversal bias shaper; digital-to-analog converter has its input connected to comparator output and its output, to first (subtracting) input of adder whose second (adding) input functions as signal input of converter whose first clock input and output is, respectively, input and output of digital filter; output of polarity-reversal bias shaper is connected to third (subtracting) input of adder; control input functions as second clock input of converter which also has third clock input connected to clock input of comparator. One-bit digital-to-analog converter and shaper are, essentially, first and second switches, respectively, connected to unlike-polarity power supplies; control inputs of switches function as respective inputs of one-bit digital-to-analog converter and shaper. EFFECT: increased speed and reduced error in analog quantity conversion to differentially modulated form at same resolution. 4 dwg

Description

 The invention relates to electronic equipment for special purposes, and more specifically to analog-to-digital converters (ADCs) of the integrating type with sigma-delta architecture, designed to work in real time and having high resolution in the elementary conversion cycle. It can be used, for example, in processing circuits (and / or measurements) of analog signals of accelerometer sensors in control systems for various moving objects to increase speed and reduce the error in converting analog quantities to a differential modulated form.

 Such ADCs [1,2] are continuously integrating converters, that is, continuously moving from one cycle to another, since the residual charge from the previous conversion is stored on the integrator. Their increased resolution, unattainable in the ADC with the conversion of sample values of the input signal, is achieved by summing the successive samples. But this also leads to their low speed. Overcoming this drawback presents a particular problem in this technical field.

Closest to the proposed invention is the known ADC with sigma-delta architecture [1], the circuit of which is shown in FIG. 1 for illustration. It contains a series-connected adder, integrator, clocked comparator and digital filter, as well as a single-digit digital-to-analog converter (DAC) included in the negative feedback circuit, the input of which is connected to the output of the comparator, and the output to the first input of the adder, the second input of which is a signal input a converter, the first clock input and output of which are the clock input and output of the digital filter, and the second clock input is the clock input of the comparator. In this case, a single-bit DAC is made on the basis of an analog switch connected to bipolar sources of a reference voltage of the same value V _REF , and the control input and output of the key are respectively the input and output of a single-bit DAC. The first and second clock inputs of the ADC provides the supply of clock pulses of frequency F _s and k • F _s, respectively, from external (for the ADC) synchronous generators.

The input signal V _IN goes to the second (summing) input of the adder and then to the integrator. Depending on the polarity of the output voltage of the integrator at the moments of arrival of clock pulses of frequency k • F _{s, the} output of the comparator takes a state of low or high level. The output signal of the comparator is fed to a digital filter and simultaneously controls an analog switch, through which one of the voltage reference sources (+ V _REF , if the logic signal at the output of the comparator is high, or -V _REF , in case of a low level) is connected to the first (subtracting ) input to the adder. The conversion process includes compensation of the average value of the input voltage V _{IN by the} voltage generated by the analog switch for a fixed time interval, including k clock cycles of k • F _s . The digital filter converts the logical sequence arriving at its input, in which the difference between the number of states with a high level and the number of states with a low level for a period of frequency F _{s is} proportional to the average value of the input signal V _IN , into the output N - bit binary code. The main disadvantage of the known Converter [1], as mentioned above, is its relatively low speed. This disadvantage cannot be eliminated by simply increasing the clock frequency k • F _s , because with increasing frequency, the conversion error increases, primarily due to the limited speed of analog keys and their switching noise. In addition, a random error in the operation of the converter can be made by the possible presence in the signal spectrum of an integrator of frequencies that fall into the passband of the digital filter, which is associated with the dependence of the nature of the voltage fluctuations at the integrator output from the input signal. Both that, and another reduce resolution of the converter.

 Thus, from the analysis of the prior art it follows that the known ADCs do not allow to solve the problem of increasing speed while maintaining the high resolution inherent in this type of ADC.

 The solution to this problem was possible due to the fact that the sigma-delta analog-to-digital converter containing a series-connected adder, integrator, clocked comparator and digital filter, as well as a single-bit digital-to-analog converter included in the negative feedback circuit, the input of which is connected to the output of the comparator, and output - to the first input of the adder, the second input of which is the signal input of the converter, the first clock input and output of which are respectively clock speed and output of the digital filter according to the invention further comprises a shaper of the alternating bias, the output of which is connected to the third input of the adder, a control input of the second clock input of the converter, which also has a third clock input coupled to a clock input of the comparator.

The essence of the invention is based on the idea put forward by the authors to obtain in each clock cycle the frequency k • F _{s of} more than 1 bit of information by introducing an additional alternating bias of the input signal with a frequency k • Fs and increasing the clock frequency of the comparator, so that the output signal of the comparator takes the form of a modulated pulses following with a frequency of k • F _s . In this case, the duration of states with a high (T ₁ ) and low (T ₀ ) signal level of the comparator in each clock cycle of frequency k • F _s is connected with the measured signal by the following relation:
(T ₁ - T ₀ ) • k • F _s • V _REF = V _IN , (1)
which is true to the discrete timing of the comparator.

The clock frequency of the comparator can be set m times higher - m • k • F _s (m is an integer, for example, m = 256 >> 1). Therefore, in contrast to the prototype, in which only one bit of information is generated in a clock cycle of frequency k • F _s , the proposed ADC generates m information pulses (i.e., M bit of information, M = log m / log 2). Therefore, in comparison with the prototype, the conversion time of the input signal to the required N-bit code is reduced by m times, i.e., the ADC performance is correspondingly increased, or N + M information bits are generated during the conversion time, i.e. the accuracy (reduction of error) of the conversion increases.

Moreover, when using an alternating bias with an amplitude of V≥2V _REF and a zero average value for the period, the oscillator output frequency of the integrator is equal to the frequency k • F _s for any input signal ranging from -V _REF to + V _REF and is outside digital filter bandwidth. This eliminates the random conversion error that is possible in the prototype when falling into this band of low-frequency components of the spectrum of the integrator signal. An advantage of the claimed ADC is also that in it the switching frequency of the analog key (as part of a single-bit DAC) is constant at any value of the input signal, therefore, the contribution from switching noise to the conversion error is stable and can be taken into account when calibrating the converter.

In the simplest case, the claimed invention can be implemented if the alternating displacement has a rectangular waveform and a zero average value over a frequency period k • F _s (for example, a meander wave), and its amplitude satisfies the condition V≥2V _REF . The alternating displacement generator can be based on an analog switch and two voltage sources of ± 2 V _REF (as shown in Fig. 2).

 The aforesaid indicates that in order to increase speed and reduce the conversion error, the presence of alternating bias is essential in combination with an increase in the clock frequency of the comparator and the existing ADC circuit, and the parameters of alternating bias can be different depending on the particular implementation and are selected from the conditions of support the necessary amplitude and zero average value of the signal at the input of the integrator for the period of the displacement frequency. Accordingly, the presence of an alternating displacement shaper in the ADC structure is essential, but not the form of its implementation. So, for example, it can be made on the basis of a controlled harmonic signal generator.

The ADC described so far is designed to work as part of a measuring complex for measuring the parameters of the input signal, which in addition to the ADC also contains the first, second, third, fourth voltage sources intended for connecting to the corresponding power inputs of a single-bit DAC and an alternating bias generator, clock frequency generators _{F s, k • F s,} m • k • F s, synchronized, for example, the clock signal with frequency m • k • F _s and intended for connection to first, second and third clock inputs AC respectively. However, it can work in standalone mode - in this case, it contains the mentioned sources and generators, which are connected to the corresponding inputs of the indicated elements of the ADC functional circuit. To extract information about the input signal, it is enough (in accordance with formula (1)) to measure the difference between T ₁ and T ₀ , that is, between the number of pulses of the clock frequency m • k • F _s per state with a high and low signal level for the period frequencies k • F _s . This can be done, for example, using a reversible counter, the counting input of which receives the clock frequency m • k • F _s , the output signal of the comparator is fed to the input of the counting sign, and the measurement time is selected by counting an integer number of periods of the clock frequency k • F _s . But for this, a computer equipped with an appropriate interface and a calculation program can also be used.

 The analysis of the essence of the invention and the features of its implementation confirms the validity of the selection of common essential features that describe the claimed ADC, and the presence of distinctive features among them indicates the compliance of the claimed invention with the conditions of patentability by novelty.

At the same time, it follows from the analysis of the prior art that the above-mentioned problem was posed by the authors for the first time, and its solution using an alternating displacement driver connected to the adder input and an additional clock input for applying clock pulses to the comparator with a frequency m times the alternating displacement frequency, which allows to correspondingly improve the performance of the ADC due to the formation of M bits of information in a clock cycle of frequency k • F _s , was not used in other solutions in this technical field. This allows us to conclude that the claimed invention meets the conditions of patentability and inventive step.

The essence of the invention described above is illustrated by way of example. In FIG. 1.2 shows the functional circuits of the ADC - respectively, the prototype and one of the embodiments of the claimed invention. In FIG. 3.4 shows timing diagrams of stresses at various characteristic points of the circuit of FIG. 2 at a constant value (Fig. 3) or stepwise change (Fig. 4) of the voltage of the signal V _IN at the signal input of the inventive converter.

 For similar elements in FIG. 1 and 2, for simplicity of comparison, similar designations were used: 1 - adder, 2-integrator, 3 - clocked comparator, 4 - digital filter, 5-one-digit DAC, 6 - alternating displacement shaper.

In addition, the following symbols are marked:
F _s , k • F _s , m • k • F _s - frequencies of clock signals supplied to the first, second and third clock inputs of the ADC;
± 2V _REF - voltage of power sources (not shown in Fig. 1,2) at the power inputs of a single-bit DAC;
± 2V _REF — voltage of power sources (not shown in FIG. 1–2) at the power inputs of an alternating displacement shaper.

 The analog-to-digital converter (Fig. 2) contains a series-connected adder 1, integrator 2, a clocked comparator 3 and a digital filter 4, as well as a single-bit DAC 5, the input of which is connected to the output of the comparator 3, and the output to the first (subtracting) input of the adder 1, the second (summing) input of which is the signal input of the converter, the first clock input and output of which are, respectively, the clock input and output of the digital filter 4, and the alternating bias generator 6, the output of which is connected to the third the (subtracting) input of the adder 1, and the control input is the second clock input of the converter, which also has a third clock input connected to the clock input of the comparator 3. In this particular embodiment of the inventive ADC, the negative feedback circuit (single-digit DAC) is shown as the first analog key (shown in Fig. 2 conventionally) connected to the first and second bipolar power sources (not shown in Fig. 2), the alternating displacement driver 6 is shown as a second analog key (n FIG. 2 is shown conditionally) connected to the third and fourth bipolar power sources (not shown in FIG. 2), and the key control inputs are the corresponding inputs of a single-bit DAC 5 and driver 6. Moreover, the first and second mentioned keys can be completely identical or have a different design .

The proposed Converter operates as follows. At the adder 1 simultaneously with the input signal V _IN and its balancing compensating signal (with the amplitude V _REF ) from the output of the single-bit DAC 5, an alternating sign offset from the output of the shaper 6 is fed, having the amplitude V = 2 V _REF and the switching frequency k • F _s . In addition, the clock frequency of the comparator 3 increases (in comparison with the prototype) by a factor of m (m is an integer, m = 256 >> 1) and is m • k • F _s Integration of an alternating displacement having a zero average value over a period leads to the fact that the output voltage of the integrator 2 periodically oscillates relative to the switching threshold of the comparator 3 with a frequency k • F _s for any value of the input signal ranging from -V _REF to + V _REF . A comparator 3, clocked by pulses of frequency m • k • F _s (synchronous with clock pulses of frequencies k • F _s and F _s ), monitors the voltage polarity of integrator 2 and generates pulse-width modulated logic signal pulses following with frequency k • F _s , the difference between the durations of high and low levels which is proportional to the value of the input signal. These pulses control the connection of the voltages ± V _REF via key 5 to the adder 1 and at the same time are the input signal of the digital filter 4. Timing diagrams illustrating the operation of the converter are shown in FIG. 3, 4. The following notation is used:
in FIG. 3 (constant value of the input signal V _IN ) - 3.1 - the output voltage of the shaper 6 alternating bias;
- 3.2, 3.4 - the output voltage of the integrator 2, respectively, at V _IN = O and V _IN = + 0.4V _REF ;
- 3.3, 3.5 - the output voltage of the clocked comparator 3, respectively, at V _IN = 0 and V _IN = + 0,4V _REF ,
in FIG. 4 (step change of input signal V _IN )
- 4.1- input signal V _IN , varying from -0.6V _REF to + 0.6V _REF ;
- 4.2 - the output voltage of the shaper 6 alternating displacement, switched with a frequency k • F _s ;
- 4.3 - the reaction of the integrator to a step change in the input signal;
- 4.4 - the output voltage of the clocked comparator 3, the clock frequency of which is 256 times the frequency k • F _s (in Fig. 4, the clock signal is not shown).

The relationship between the parameters of the output logical signal of the comparator 3 and the input signal V _{IN is} described by the relation (1). It is possible to measure the difference T ₁ -T ₀ and, therefore, extract information about the input signal by calculating the difference in the number of clock pulses m • k • F _s per state with a high and low signal level at the output of the integrator 3 over a period of frequency k • F _s (for example, using a reversible counter, as mentioned above).

 Since in the manufacture of converters in which the claimed invention is implemented, known elements and blocks, the production of which is mastered by the industry, can be used, this suggests that the claimed invention meets the patentability conditions for industrial applicability.

The described embodiments of the claimed invention are given by the authors only for illustration: they do not exhaust the essence of the invention. Other specific implementations are possible. So, the second input of the adder to supply the input signal can be subtracting, then the first input of the adder to supply the compensating signal must be summing to provide the described compensation. At the same time, to distinguish information about the input signal, the interval difference T ₁ - T _{0 is used} . In addition, the measured value can be not only voltage, but also current. In this case, the input signal is balanced (compensation of its average value) and alternating bias is applied by connecting calibrated current sources (with the same ratios of their values as for the voltage sources described above) to the adder via a single-bit DAC and a shaper (made, for example, in as analog keys) and using an adder of the corresponding type with a current / voltage converter at its output. The remaining elements of the circuit can be left the same.

 Therefore, the above or other examples of a specific embodiment of the invention cannot (in view of their diversity) limit the essence of the invention, which is most fully described in the attached claims.

Literature
1. Analog Devices Inc. 1993. Applications reference manual. Page 20-4. Sigma-delta convertors.

 2. Horowitz P, Hill W. The art of circuitry. V.2, - Mir, 1984, p. 66.

Claims (1)

 Sigma-delta-analog-to-digital converter containing a series-connected adder, integrator, clocked comparator and digital filter, as well as a single-digit digital-to-analog converter, the input of which is connected to the output of the comparator, and the output to the first input of the adder, the second input of which is the signal input of the converter , the first clock input and output of which is, respectively, the clock input and output of the digital filter, characterized in that it further comprises an alternating driver the first offset, the output of which is connected to the third input of the adder, and the control input is the second clock input of the converter, which also has a third clock input connected to the clock input of the comparator.

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