RU2447577C1 - Sigma-delta analog-to-digital converter with galvanic isolation on condensers and manchester ii coders - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device contains analog part of sigma-delta ADC unit including sigma-delta modulator and Manchester II coder unit, digital part of sigma-delta ADC unit including Manchester II decoder unit and two isolating condensers.

EFFECT: higher interference resistance in the process of analog signal conversion into digital signal due to introducing isolating condensers, Manchester II coder and Manchester II decoder into signal circuits connecting analog and digital parts of classic sigma-delta ADC.

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Description

The invention relates to devices for analog-to-digital conversion and is intended to build telemetry systems and digital signal processing.

The prior art knows a huge number of chips of analog-to-digital conversion (ADC). They differ in the principle and resolution of the conversion, the number of channels, the type of user interface, electrical characteristics. Telemetry systems that combine a digital processor core and analog peripheral units such as an ADC on a single chip are currently popular. At the same time, external measuring devices (sensors) are often located at a considerable distance. In such systems, it is necessary to galvanically decouple the analog ADC channels from the internal buses of the microcontroller.

Closest to the claimed invention is the architecture of the chip AD7401 firm Analog Device. This microcircuit belongs to the sigma-delta ADC class, the principle of operation of which is described in the document [1]. Isolation is ensured by transformer interchanges. The signal from the sigma-delta modulator is input to the encoder, which converts it into a sequence of pulses of 1 ns duration according to the following rules:

- the leading edge corresponds to 1 pulse;

- 2 pulses correspond to the trailing edge.

The secondary winding of the transformer reproduces the pulses of the encoded sequence, and the decoder restores the original signal and transfers it to the input of the digital filter. Similarly, isolation is provided along the clock line. The main disadvantage of this implementation is the presence of interference in the output signal due to the presence of inductance in the transformer coils.

The technical result of the claimed invention is to increase noise immunity in the process of converting an analog signal to digital in a given range.

The technical result is achieved by the fact that the sigma-delta analog-to-digital converter (ADC) with galvanic isolation on capacitors and encoders Manchester II contains a block of the analog part of the sigma-delta ADC, including a sigma-delta modulator and a block of the encoder Manchester II, the digital part of the sigma the delta ADC, including the Manchester II decoder block and a digital filter, wherein the sigma-delta modulator consists of the first and second adders, the first and second integrators, a comparator and a key, while the first input of the first adder, which is I am the first input of the sigma-delta modulator, the measured analog signal arrives, the input of the first integrator is connected to the output of the first adder, the first input of the second adder is connected to the output of the first integrator, the input of the second integrator is connected to the output of the second adder, the first input of the comparator is connected to the output of the second integrator, a clock signal is supplied to the second input of the comparator, the output of the comparator, which is the output of the sigma-delta modulator, is connected to the first input of the Manchester II encoder block and with a key with second inputs of the first and second adders, respectively, the output of the Manchester II encoder block is connected through the first decoupling capacitor to the first input of the Manchester II decoder block, the output of which is connected to the first input of the digital filter, the digital filter output is the output of the claimed device, an external clock signal is received to the second inputs of the Manchester II decoder block and the digital filter, respectively, and also through the second decoupling capacitor to the second inputs of the sigma-delta modulator and the Manchez encoder block ter II, respectively.

The structural diagram of the claimed invention is presented in figure 1, where:

1. Block analog sigma-delta ADC;

2. Sigma-delta modulator;

3. Block encoder Manchester II;

4. The first decoupling capacitor;

5. The second decoupling capacitor;

6. Block digital sigma-delta ADC;

7. Block decoder Manchester II;

8. Digital filter.

The structural diagram of the sigma-delta modulator (item 2 in figure 1) is presented in figure 2, where:

9. The first adder;

10. The first integrator;

11. The second adder;

12. The second integrator;

13. Comparator;

14. The key.

Figure 3 presents the timing diagrams of work.

The principle of operation of the claimed invention is as follows.

The block of the analog part of the sigma-delta ADC (1), consisting of the sigma-delta modulator (2) (see Figs. 1, 2) and the block of the Manchester II encoder (3), converts the input analog signal into a digital binary data stream, allows you to transmit digital binary stream to the digital part without reference to the potential of the common chip wire. The digital sigma-delta ADC block (6), consisting of the Manchester II decoder block (7) and a digital filter (8), implements the conversion of a 1-bit sequence from the sigma-delta modulator (2) into 14-bit samples. The digital filter is designed to convert the signal sequence into a multi-bit code. The isolation barrier divides the analog (block of the analog part of the sigma-delta ADC (1)) and digital (block of the digital part of the sigma-delta ADC (6)) parts that are connected by two circuits: the signal line of the clock frequency and the data line. The main element of the isolation barrier is the first and second decoupling capacitors (4, 5), which pass only the high-frequency component of the signals passing through them and filter out the constant component. This is enough to provide galvanic isolation along the line of the clock signal, because the useful part of the clock signal is high frequency. The data signal, in turn, is an arbitrary waveform and can be represented in the entire frequency range. Accordingly, to ensure the preservation of useful information transmitted over the data line, additional measures must be taken.

When the logical “exclusive or” operation is performed on the clock frequency signal and the data line signal, the result is a variable frequency signal that carries useful data line information. This coding method is called Manchester II and allows you to overcome the isolation barrier, while retaining the necessary information.

Work on the schemes (see figure 2 and figure 3) is as follows.

The clock signal (A) directly goes to the digital sigma-delta ADC block, and also through the second decoupling capacitor to the analog sigma-delta ADC block (B). A sigma-delta modulator, based on the input analog signal (C) and the clock signal (B), forms a modulated data sequence (D). The data sequence (D) is obtained as follows.

The analog signal (C) is fed to the input of the first adder (9), in which the feedback signal is subtracted from it, also fed to the input of the first adder. The signal from the output of the first adder goes to the input of the first integrator (10), where it accumulates. The signal from the output of the first integrator is fed to the input of the second adder (11), in which the feedback signal is subtracted from it (see Fig. 2), also fed to the input of the second adder. The signal from the output of the second adder is fed to the input of the second integrator (12), where it accumulates. The signal from the output of the second integrator is fed to the input of the comparator (13), where the clock frequency signal (V) also arrives. If the voltage value at the output of the second integrator is positive, the output signal of the comparator is "1", if negative, then "0". The comparator output is updated by a clock signal. The output signal of the comparator is the output signal of the sigma-delta modulator. In addition, the output signal of the comparator controls the key (14) in the feedback circuit, if the comparator signal is "1", the feedback signal is + U _op. (reference voltage), if "0", then -U _op. . This sequence is fed to the input of the Manchester II encoder block, which also receives the clock signal (B). The Manchester II encoder block performs an exclusive or operation on input signals. The converted sequence from the output of the Manchester II (E) encoder block through the first decoupling capacitor is fed to the input of the Manchester II (F) decoder block, which is a D-trigger clocked by a clock signal (A). The reconstructed sequence from the output of the Manchester II (G) decoder block is fed to the input of the filter, with the transfer characteristic (Sin (x) / x) ³ , which generates an output 16-bit code (H).

During the operation of this sigma-delta ADC with a user interface isolated by direct current from the analog channel, the following characteristics were obtained:

- isolation by direct current (limit voltage 40 V) of the analog path from the user interface;

- output reports - 12-16 digits;

- sampling frequency up to 100 kHz;

- supply voltage 3.3 V ± 20%;

- input voltage range ± 2 V.

Bibliography

1. Max W. Hauser, "Principles of Oversampling A / D Conversion", Audio Engineering Society, Vol. 39, No. 1/2, 1991

Claims (1)

The Sigma-Delta analog-to-digital converter with galvanic isolation on capacitors and encoders Manchester II contains a block of the analog part of the sigma-delta ADC, including a sigma-delta modulator and a block of the encoder Manchester II, a block of the digital part of the sigma-delta ADC, including the block of the Manchester II decoder and a digital filter, while the sigma-delta modulator consists of the first and second adders, the first and second integrators, the comparator and the key, while the first input of the first adder, which is the first input of the sigma-delta modulator, the measured analog signal, the input of the first integrator is connected to the output of the first adder, the first input of the second adder is connected to the output of the first integrator, the input of the second integrator is connected to the output of the second adder, the first input of the comparator is connected to the output of the second integrator, the clock frequency signal is fed to the second input of the comparator , the output of the comparator, which is the output of the sigma-delta modulator, is connected to the first input of the Manchester II encoder block and feedback through the key with the second inputs of the first and second sum torus, respectively, the output of the Manchester II encoder block is connected through the first decoupling capacitor to the first input of the Manchester II decoder block, the output of which is connected to the first input of the digital filter, the digital filter output is the output of the claimed device, an external clock signal is supplied to the second inputs of the Manchester II decoder block and digital filter, respectively, as well as through the second decoupling capacitor to the second inputs of the sigma-delta modulator and encoder block Manchester II, respectively.

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