SU1499494A1 - Clocking arrangement - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase speed. The device contains a phase detector 1, a DC amplifier 2, a proportional-integrating filter 3, adders 4 and 5, a controlled oscillator 6, a differentiating unit 7, a limiter 8, a threshold unit 9, a shaper 10 counting signals, a reversible counter 11, a DAC 12 and 13, controlled attenuators 14 and 15, key 16, storage unit 17, A / D converter 18, accumulator 19, pulse generator 20, amplitude meter 21 and averaging unit 22. The goal is achieved by providing a more accurate match between frequency detuning and voltage eliminating it. 2 Il.

Description

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The invention relates to telecommunications and can be used in information transmission systems.

The purpose of the invention is to improve the speed,

Fig. 1 shows a structural electrical circuit of a synchronization device; FIG. 2 shows timing diagrams of signals explaining the operation of the synchronization device.

The synchronization device contains a phase detector (PD) 1, a direct current amplifier 2 (UFD), a proportional-integrating filter (UIF) 3, 15 first and second adders 4 and 5, a controlled oscillator 6, a differentiating unit 7, two-way symmetrical below limiter 8, threshold unit 9, shaper 10 signature counts, reversible counter (PC) 11, first 12 and second 13 digital-to-analog converters (D / A), first 14 and second 15 controlled attenuators, key 16, storage unit 17, 25 analog-to-digital converter 18, drive 19, generator 2 0 pulses, 21 amplitude meter, averaging unit 22o /

The synchronization device operates in 30 s as follows.

When the frequency mismatch is less than the bandwidth of the phase locked loop (FAL) containing PD 1, DCF 2, SIF 3, the first 35 adder 4 and the controlled oscillator 6, the latter is put into synchronous mode of operation due to the operation of this PLL ring ,

When frequency detuning is not performed by the FAP ring, a bit voltage appears in PD 1 (Fig. 1 and 2a). This voltage is periodic in nature, and the first harmonic of this voltage is already limits of transparency of the unit investment fund So, therefore, this beat voltage does not enter the input of the controlled generator 6 due to the suppression in unit investment fund 3 and the PLL ring does not operate.

Due to the sawtooth characteristics of PD 1, the beating voltage contains areas with a large steepness, which indicate the presence of a frequency mismatch. These areas are separated by means of a differentiating unit 7 (Fig. 2b), the output voltage of which is in the form of short

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pulses of one polarity. At another frequency detuning sign, the polarity of the pulses is opposite,

From the output of the differentiating unit

7 pulses arrive at the limiter 8, the shape of the pulses at the output of which is similar to the shape of the input pulses, but those input pulses whose amplitude is less than the threshold voltage will not pass to the output of the limiter 8,

From the output of the limiter 8, the pulses go simultaneously to the meter 21. and the driver 10, which, after appropriate normalization and conversion, sends pulses of one polarity, for example, to. The SM 11 input and the other polarity are sent to the PC 11.

The last digitally accumulated information about the number of incoming pulses, which in the second DAC 13 is converted to analog form (Fig. 2c). This step-shaped voltage is varied in size by the first controlled attenuator 14 so that after the second adder 5 monotonous linearly varying voltage (fig 2g)., This voltage goes to key 16, which is unsealed by generator 20 at the time of T analysis. The analysis interval is determined by a constant low-pass filter time or integrating integrator in PD 1,

To maintain the monotony of the voltage (Fig. 2d), the transmission coefficient of the first controlled attenuator 14 must be set proportionally to the amplitude of the beats. At the same time, regardless of the frequency detuning at the end of the analysis interval T at the output of the key 16, the signal is of the same level. The threshold unit 9 is set to this level. After the last one triggers, its output voltage (Fig 2d) changes inversely proportional to. rationally, the average amplitude of the beats in the second controlled attenuator 15; Then this voltage, the value of which is proportional to the initial frequency detuning, is stored in the storage unit 17,

Next, the analog voltage is. is digitized using an analog-to-digital converter 18 and accumulated in accumulator 19. The output code of the latter contains information on all the frequency detuning changes that have occurred since the synchronization device was turned on. Using the first D / A converter 12, the digital code of the accumulator 19 is converted to analog voltage, which is summed up in the first adder 4 with the FAL error voltage and controls the frequency of the controlled oscillator 6,

The operation of the key 16 of the storage unit 17 is synchronized by the generator 20, which forms a gating pulse (FIG. 2e) of duration T and a latch pulse of the storage unit 17 (FIG. 2G) of duration f which is selected from the condition of all operations associated with tuning the frequency of the controlled oscillator 6. The oscillator 20 operates in the standby mode and is triggered by the meter 21, which is an amplitude latch with a corresponding standardization of the output voltage (Fig. 2h). Since the threshold unit is started only in the presence of beats, the launch of the generator 20 occurs mainly in the presence of frequency detuning,

To improve the accuracy of setting the frequency of the controlled oscillator 6 under the action of interference, the transmission coefficient of the second controlled attenuator 15 is set by the voltage from the averaging unit 22, which generates a voltage averaged over the analysis period T, which provides a more accurate match between the frequency detuning and stress, its elimination

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Claims (1)

Invention Formula A synchronization device containing a series-connected drive, a first digital-to-analog converter, a first adder, a controlled oscillator, a phase de0 five 0 five 0 five 0 five tector, DC amplifier and proportional-integrating filter, the output of which is connected to the second input of the first adder, serially connected counting generator, reversible counter and second digital-to-analog converter, as well as the differentiating unit and the second adder, whose inputs are connected to the output of the phase detector, an analog-to-digital converter and a pulse generator, the second input of the phase detector being the input of the device, which is different in that, in order to increase the speed Twi, entered in series connected two-sided symmetric lower limiter, applique meter and the first controlled attenuator, the output of which is connected to the second input of the second adder, serially connected averaging unit, the second controlled attenuator and the storage unit, the output of which is connected to the output through the analog-to-digital converter to the accumulator input, a series-connected key and a threshold unit, the output of which is connected to the information input of the second controlled attenuator, with this the output of the amplitude meter is connected to the inputs of the averaging unit and the pulse generator, the first and second outputs of which are connected respectively to the control inputs of the storage unit and the key, whose information input is connected to the output of the second adder, the input and output of the two-way balanced lower limiter are connected respectively to the output of differentiator of the unit and the input of the counting signal generator, - and the output of the second digital-analog converter is connected to the information input of the first control unit. go attenuator. a b l BUT BUT X / ITv 2