RU2207719C1 - Facility of phase automatic clock frequency control of analog-to-digital converters in multichannel systems of seismic data acquisition - Google Patents

Abstract

FIELD: message transmission systems with conversion of analog signals to digital form on basis of delta modulation, multichannel telemetering systems of seismic data acquisition. SUBSTANCE: technical result of invention lies in such organization of automatic clock frequency control that operation of all ADCs incorporated in multichannel telemetering system of seismic data acquisition is ensured and authenticity of transmission of seismic information is raised. Facility of phase automatic clock frequency control of analog-to-digital converters in multichannel system of seismic data acquisition includes clock generator coupled to clock input of digital filter and delta modulator of analog-to-digital converter connected in series. According to invention facility incorporates first D flip-flop to which clock input interrogation signal from communication line arrives and to which information input signal of readiness of analog-to-digital converter comes. Clock generator includes quartz generator which output is coupled to clock input of second D flip-flop and to clock inputs of two counters-frequency dividers connected in series. Information input of first counter-frequency divider is connected to output of first D flip-flop and its load input is connected to output of second D flip-flop. Information input of the latter is connected to overflow output of second counter-frequency divider whose one position output is output of clock generator and is coupled to clock inputs of digital filter and delta modulator. EFFECT: raised authenticity of transmitted seismic information. 1 dwg

Description

 The invention relates to techniques for transmitting messages using the conversion of analog signals to digital form based on delta modulation and can be used in multi-channel telemetry systems for collecting seismic data.

 Known highly informative analog-to-digital Converter using the principles of delta modulation for seismic studies (RF patent 2128880, N 03 M 3/02). This device includes a clock associated with a delta modulator containing an input device, a frequency divider, a subtractor, a comparator, a polarity converter, an integrator control device, a controlled integrator. In accordance with well-known ADC circuitry, the output signal Y of the delta modulator is then fed to a digital filter (not shown in the description), from which the final signals of analog-to-digital conversion and readiness signals for reading data (DRDY) are taken. This ADC organization cannot provide high reliability, reliability, and no loss of reception of seismic information in multichannel telemetry systems for collecting seismic information, since the speed of the ADC directly depends on the frequency of the clock generator of each channel. Since the frequencies of the generators can vary, then the time interval between the moment of the ADC polling and the readiness of its data gradually changes. As a result of this, if the duration of the session is long, two types of errors can occur: an overflow error when the ADC prepared the next batch of data and the previous one was not read; loan error, when the data is not yet ready at the time of the ADC survey. These errors in the seismogram lead to data loss (a dip at 0) or to an instantaneous abrupt change in the phase of the input signal (step), which leads to an error in the transmission of seismic information and, therefore, reduces the reliability of multichannel seismic data acquisition systems.

 The objective of the invention is the organization of tuning the clock frequency of the ADC so as to ensure in-phase operation of all ADCs included in the multichannel telemetry system for collecting seismic data, and to increase the reliability of the transmission of seismic information.

 The problem is solved in that the phase locked loop device of the analog-to-digital converters in multichannel seismic data acquisition systems, including a clock connected to the clock inputs of a digital filter and a delta modulator of an analog-to-digital converter, according to the invention, further includes a first D -trigger, to the clock input of which a polling signal is received from the communication line, and to the information input - the signal of readiness of the analog-to-digital conversion At the same time, the clock generator includes a crystal oscillator, the output of which is connected to the clock input of the second D-trigger and the clock inputs of two counter-frequency dividers connected in series, while the information input of the first counter-frequency divider is connected to the output of the first D-trigger, and boot input - with the output of the second D-flip-flop, the information input of which is connected to the overflow output of the second counter-frequency divider, one of the bit outputs of which is the output of the clock generator and is connected with clock inputs of digital filter and delta modulator.

 The essence of the invention lies in the fact that to control the ADC ready signal, the conversion frequency is accelerated or decelerated by a corresponding change in the frequency of the clock generator.

 The drawing shows a structural diagram of a device according to the invention.

 The phase-locked loop device for the clock frequency of analog-to-digital converters in multi-channel seismic data acquisition systems contains an analog-to-digital converter (ADC) 1, including a delta modulator 2, connected to a digital filter 3. The clock inputs of the delta modulator 2 and digital filter 3 are connected to the output clock 4. The output of the ADC 1 ready signal is connected to the information input of the first D-flip-flop 5, the clock input of which receives polling signals from the communication line 6. Clock 4 includes a crystal generator 7, the output of which is connected to the clock inputs of sequentially counted frequency dividers 8 and 9 and the second D-trigger 10. The information input and output of the D-trigger 10 are connected respectively to the output of the overflow signal of the frequency counter-divider 9 and the input of the counter load signal frequency divider 8. The output of the clock generator 4 is one of the bit outputs of the counter-divider frequency 9.

 The device according to the invention work as follows.

 In multi-channel seismic information acquisition systems, the ADC 1 is polled, the input of which analog seismic signals are received, occurs at the moment of passing through the communication signal 6 the polling signal ("PACK"), which contains the data of the ADC 1, the channels previously polled, and has a set for this system clock frequency. The signal "PACK" is supplied to the clock input of the D-flip-flop 5, to the information input of which the ADC 1 is ready. The state of the D-flip-flop 5 indicates which of the indicated signals came first, and which later, that is, there is an indirect comparison of the clock frequency ADC 1 of this channel with the clock frequency set in the system. If the output is "0", (necessary) acceleration of the clocks occurs, if the output is "1" - deceleration. The clock frequency of the ADC 1 is formed by dividing the reference frequency of the crystal oscillator 7 using two series-connected counters-dividers 8 and 9. Counters-dividers 8 and 9 operate in synchronous mode. When the first counter-divider 8 is overflowed, an overflow signal (high-level pulse) appears at its output Cout, by which the counter-divider 9 switches. When the counter-divider 9 is overflowed, the overflow signal Cout goes to the information input of the D-trigger 10, at the output of which a correction signal is generated with a duration of one clock cycle frequency, which is fed to the “LOAD” input of the counter-divider 8. When this signal appears, the counter-divider 8 from state “00” goes into state “00” if output D trigger 5 s Ignal "1", that is, skips one beat. If the output of the D-flip-flop 5 signal is "0", then the counter-divider 8 goes into state "10", that is, it goes two steps forward, skipping state "01". this is the correction (deceleration or acceleration) of the pulse repetition period, taken from the corresponding bit output of the counter-divider 9 and specifying the clock frequency of the ADC 1. These pulses are fed to the clock inputs of the delta modulator 2 and digital filter 3. Thus, the phase-locked loop ADC 1, as a result of which the readiness signals of all ADC 1 included in the multichannel seismic data acquisition system are adjusted to the moment of data polling set in the multichannel system.

The device according to the invention is implemented in a multichannel seismic station STS-24R, made on 6-channel field modules, using standard microchips CK5321BL-1 (delta modulator, digital filter) and EPF10K10L 184-4 (D-flip-flops and divider counters). The accuracy of quartz oscillators (for example, HG-2012 BX-16.384 MHz) is ± 50 • 10 ^-6 , while their mutual instability in a multi-channel system can reach ± 100 • 10 ^-6 . Before the introduction of a phase-locked loop system of the clock frequency of analog-to-digital converters, errors were already observed when transmitting 10,000 samples of seismic information. The use of the device according to the invention made it possible to conduct recording sessions of up to 200,000 or more samples per channel without errors, as well as without the need to restart field modules before each observation session.

Claims (1)

 A phase-locked loop device for the clock frequency of analog-to-digital converters in multichannel seismic data acquisition systems, including a clock connected to the clock inputs of a digital filter and a delta modulator of an analog-to-digital converter, analog seismic signals are input to the input of the delta modulator, and the output of analog -digital converter is the output of the device into the communication line, characterized in that it includes the first D-trigger, the clock input of which is it receives a polling signal from the communication line, and to the information input, the readiness signal of the analog-to-digital converter, and the clock generator includes a crystal oscillator, the output of which is connected to the clock input of the second D-trigger and the clock inputs of two frequency divider counters connected in series, while the information input of the first counter-frequency divider is connected to the output of the first D-trigger, and its boot input is connected to the output of the second D-trigger, the information input of which is connected to the overflow output of the second tchika-frequency divider, one output bit which is the output of the clock generator and is connected to the clock input of the digital filter and the delta modulator.