SU1663772A1 - Noise-like signal receiver - Google Patents

Abstract

This invention relates to a technique for transmitting information using multi-site noise-like signals. The purpose of the invention is to improve noise immunity. The device contains on the transmitting side a frequency grid generator 1, multiplexers 2 and 3, information source 4, generators 5 and 6 of pseudo-noise sequence, clock generator 7, mixer 8, adder 9, shift register 10 and mixer 11, and on the receiving side a synchronizer 12, counter 13, frequency grid generator 14, 15 clock pulse generator, mixer 16, amplitude detectors 17, matched filters 18 and 19, ADC 20, shift registers 21, threshold unit 22, RS flip-flop 23, element I 24 and block 25 select the maximum. The goal is achieved by reducing the false positives of the threshold unit 22. 2 Il.

Description

The invention relates to the transmission of information using multipoint noise-like signals and can be used for communication over radio and driving channels.

The purpose of the invention is to increase noise immunity by reducing the false alarms of threshold elements.

Figure 1 shows the structural electrical circuit of the device proposed; 2 shows timing diagrams for the operation of the device.

The device contains on the transmitting side a frequency grid generator 1, first and second multiplexers 2, 3, information source 4, generators 5, 6 pseudo-noise sequence, 7 clock pulses, mixer 8, adder 9, shift register 10, mixer 11, on a straight line synchronizer 12 side, counter 13, frequency grid generator 14, 15 clock pulse generator, mixer 16, amplitude detectors 17, matched filters 18,

19, analog-to-digital converters 20, shift registers 21, threshold unit 22, RS trigger 23, AND 24 and maximum selection block 25,

The device works as follows.

In the initial state, the device generators 5 and 6 are in the initial state, i.e. with the arrival of signals at the clock inputs, they generate elements of the pseudo-noise sequence (PN sequence), starting from the first. After this, the shift register 10 and the counter 13 are reset to zero, the clock pulse generator 7 is turned off, a binary is set at the outputs of the information source 4 (the bit code, whose I and m bits are sent to one group of multiplexer inputs 2 3 Generator: 1 and 14, generate 2 tons outputs harmonic signals with frequencies according to the rule

cl

with

about about with VJ

Vj

Yu

frfoHt Af,, ... 2m-1, I with

where f0 is a fixed frequency;

Tc - the duration of the signals, and on the M-th output - the harmonic signal of a fixed frequency tm.

Figure 2 shows the signals at one (Fig.2A) and another (Fig.26) outputs of the clock generator 7, at the outputs of one (Fig.2g) and another (Fig.2b) generators 5, b, at the output of one multiplexer 3 (Fig. 2d), at the outputs of one (Fig. 2g) and another (Fig. 2e) mixers 11.8, at the output of the matched filter 19 (Fig. 2h), at the output of the matched filter 18 (Fig. 2i), on one input of which receives a harmonic signal with a frequency equal to the frequency of the information signal at the outputs of the other matched filters 18 (Figure 2k),

Turn on the generator 7 clock pulses. It produces a sequence of pulses following at intervals At. Under the action of signals from its other output, the generators 5 and 6 produce elements of the binary PNG information and synchronizing signals, respectively. From the output of the generator 6, the elements of the synchronization code are fed to one input of the mixer 12, to another input of which the signal from the Mth output of the generator 1 of the frequency grid is received, From the output of one generator 5, the PSW information signal goes to one input of the shift register 10. Under the action of each signal coming from the other generator output 7 clock pulses to the clock input of the shift register 10, the latter shifts its contents by one cell and reads the next code element to its one input from the generator 5 output. the output of the shift register register 10 is fed to another group of inputs of one multiplexer 3, which passes to the output a signal from that input, which is determined by the binary code that goes to its one group of inputs. In this way, a controlled delay of the information signal is performed.

From the first 2m outputs of the frequency grid generator 1, the signals arrive at another group of inputs of another multiplexer 2, the output of which receives a signal from the input defined by the m - bit code to its one group of inputs. In this way, a controlled selection of the carrier frequency is made. The signal from the output of one multiplexer 3 is fed to one input of the mixer 11, the other input of which receives a signal from the output of another

multiplexer 2. From the output of one mixer 11, the signal goes to one input of the adder 9, to the other input of which a signal comes from the output of the other mixer 8, and the signal from the output of the adder 9 enters the data transmission channel. After every / N + 2 -1 / ticks on another generator output 7 clock pulses, where At is the number of code elements of the information signal; Tc

10 is its duration, the clock pulse generator 7 generates a signal at one output, under the action of which the source 4 of information sets a new (+ t) -bit binary code at its outputs,

15, generators 5 and 6 go to the initial state, and shift register 10 is zeroed. Further, the operation of transmitting side 1 is repeated. Duration of the sync signal. In the receiving part signals from the outputs

20 of the generator 14 is fed to one input of the mixers 16, to the other inputs of which the sum of the syncro and information signals from the data transmission channel is received, also to the input of the synchronizer 12,

25 with the output of which control signals are fed to the inputs of generators 14, 15. From outputs 2m of mixers 16 signals through one matched filters 18 and amplitude detectors 7 go to one of the inputs of analog-digital converters 20. From the output of one of the mixers 16, to one input from the output of the generator 14 receives a signal with a frequency fm, through another matched filter 1§ and amplitude

35, the detector 17 receives a signal at the threshold unit 22, the output of which at the time of arrival of the clock signal generates a pulse arriving at one input of the RS flip-flop 23. After its action, the element AND 24 transmits signals arriving at its other input from the generator output 15 clock pulses .

Under the influence of each signal from the output of the AND 24 analog-to-digital converters 20, take samples of incoming signals at their single inputs and feed the conversion results to one, the inputs of shift registers 21, shifting their contents by one cell and writing the next code to their first cell counter 13 increases its content by one. When the contents of counter 13 become equal to L, it will null and give a signal to the control input of block 25

55 select the maximum and the input of the trigger 23, which stops the transmission of the pulse generator 15. clock pulses to its output. The maximum selection block 25 in this case reads the signals arriving at its inputs from the outputs of the cells of all the registers 21

shift, determines and sets at its output the input number with the maximum code. This number clearly corresponds to the information transmitted.

Claims (1)

Formula of gain A device for receiving noise-like signals, containing n reception channels and a synchronization channel, each reception channel consists of a mixer, the output of which is connected to the input of a matched filter, and the synchronization channel consists of a mixer, the output of which is connected to the input of a matched filter and threshold unit, as well as a counter and the decision block and the frequency grid generator, the output of which is connected to the heterodyne inputs of the mixers n of the reception channels and the synchronization channel, the inputs of the mixers of all the reception channels and the synchronization channel us and are input device, characterized in that, in order to increase noise immunity by reducing false positives threshold block administered timing unit, clock generator, connected in series RS-trigger and And, and serially connected amplitude detector, analogue to digital converter and shift register are entered into each reception channel, an amplitude detector is inserted into the synchronization channel, its input is connected to the output of the matched filter, and the output is connected to the input of the threshold unit, the output of which is connected to the first the input of the RS flip-flop, the second input of which is connected to the output of the counter, in each reception channel the output of the matched filter is connected to the input of the amplitude detector, and the output of the shift register is connected to the corresponding ode decisive unit, the synchronizer output is connected to the clock inputs of the frequency grid generator, and the clock pulse generator, the output of which is connected to the second input of the element And whose output is connected to the inputs of the analog-digital converter, and the shift register, the reception channels and the input Reset counter and the synchronizer input is connected to the input of the device, while the decision block is made in the form of a maximum selection block. 1