KR900002636B1 - A apparatus for synchronizing transmission clock signal - Google Patents

Abstract

The circuit for peventing the transmission loss of PCM data comprises a phase comparator/counter (1) comparing and counting the input reference clock signal (RF) during 1 period of a comparative clock (VF), a speed comparator (2) determining the phase speed by comparing the temporarily counted value of the counter with reference value (VS), an adder/subtractor (3) compensating the phase difference, a D/ A converter (4) converting the digital output of the adder to analog signal, a voltage controlled qualitz oscillator (5) generating the transmission clock, and a divider (6) dividing the transmission clock for providing to the phase comparator/counter.

Description

Transmission clock synchronizer of digital exchange

1 is a block diagram of a transmission clock synchronizer of the present invention.

2 is a waveform diagram illustrating a comparison process of a phase comparator, which is a transmission clock synchronizer of the present invention.

* Explanation of symbols for main parts of the drawings

1: Phase Comparator 2: Dimension Comparator

3: deceleration counter 4: D / A converter

RF: Input Reference Clock VF: Comparison Clock

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a transmission clock synchronous device of a digital exchange which communicates with a pulse code (PCM). In particular, the transmission data is synchronized with a phase locked loop to prevent the loss of the data signal generated when transmitting with a pulse code. The present invention relates to a transmission clock synchronizer of a digital exchange, which enables transmission without loss.

In general, during the exchange period interconnected in the switching network that performs the exchange function by pulse code, the digital multi-accounting device transmits and receives a function.

Therefore, pulse code, which is a transmission signal of digital heavy accounting device, is sent to mutually promised transmission clock, and the receiving side extracts the clock from the received signal and receives the data as the clock to use as exchange information. In the case of the mutual synchronization method, the extracted reception clock may be used as a reference clock for synchronization of the self-exchanger in order to realize the network synchronizer of the digital switching network when the clock is a higher station or an equivalent station clock.

However, in a conventional electronic exchange, a switch in which the internal pulse code of the exchange is 32 channels and the transmission method by the multi-accounting device is 24 channels is transmitted from the 32 channel internal signal to the 24 channel signal. If it is not synchronized, data loss occurs, and thus, a transmission clock synchronized with an internal clock is required to transmit the signal without loss.

Therefore, the analog low pass filter was used to obtain the synchronized transmit clock, but the phase change factor of the oscillation clock occurred due to the change of the characteristics of the analog low pass filter due to the environmental changes such as ambient temperature, voltage fluctuations, and humidity. There are difficulties in filter design and complicated circuit configuration.

In order to solve the above drawbacks, the present invention provides a synchronization method for generating a transmission clock for synchronization of a digital switching network. The internal clock of the 32 channel exchanger is synchronized with a phase-locked loop to prevent loss of data signals and to provide an economical transmission clock synchronizer by converting and transmitting the signal from the 32 channel internal signal to the 24 channel without loss. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Phase comparison counter (1) which compares and counts the 16.384MHZ reference clock signal (RF) for one cycle of the 8KHZ clock signal (VF) divided by the divider (6) to generate a clock of 1.544MHZ, which is the transmission clock of the exchanger. After reading and storing the value counted by the phase comparison counter 1 and comparing the value with a certain value VS to the dimension comparator 2 and the dimension comparator 2 to determine the slow and fast phase Converts the digital output value (that is, 12-bit digital signal) from the accelerometer (3) and the accelerometer (3) to control the input from the 12-bit digital output value corresponding to the generated frequency to the least significant 1 bit. 8KHZ of 1.544MHZ transmission clock generated by the voltage controlled crystal oscillator 5 and the voltage controlled crystal oscillator 5 which control the analog value of the D / A converter 4 to generate a clock synchronized with the input reference clock. The reference clock signal RF The frequency divider 6 divides a low frequency that can be counted for one period from the rising edge of the 8KHZ clock signal VF to the next rising edge. Same as

First, in the phase comparison counter 1, an input pulse of the reference clock signal RF 16.384MHZ as shown in FIG. 2B is generated in order to generate a clock of 1.544MHZ, which is a transmission clock of the exchange. 1 week period from the rising edge (Edge) of the 8KHZ clock signal (VF) to the next rising edge as shown in (b) of FIG. 2 in which the 1.544MHZ transmission clock generated at It counts the number of bits of the 16.383MHZ reference clock signal (RF) input during 125US, which is an 8KHZ period that divides the generation clock, which continues in the 8KHZ period.

This counted value is input to the dimension comparator 2 as shown in (e) of FIG. 2, and the input count value is read from the dimension comparator 2. The counted value of the ground phase comparison counter 1 is erased and continues to count as shown in (d) of FIG. 2 to continuously compare the phases.

The dimension comparator 2 reads the value counted by the phase comparator 1, memory latches it, and compares the value with a certain value VS.

Here, the predetermined value VS may vary according to the count initial value RS set in the phase comparison machine 1 and becomes 2048 (decimal) of 2 ¹¹ when the initial value RS is 0.

In other words, if the frequency of the input reference pulse of the phase locked loop circuit is set to the input reference clock signal RF, and the signal frequency of the phase comparison clock that divides the generated clock is 8KHZ clock signal (VF), VS = RF / VF + RS. Also, in the dimension comparator 2, the value counted by the phase comparator 1 is compared with a predetermined predetermined value VS, and when the value is large, the phase of the generated frequency is slow, and when the value is opposite, the phase is fast and the phase is fixed. It is a state.

That is, when the phase comparator 2 judges that the phase is slow and fast, and inputs the determination signal to the input terminal of the accelerometer 3 to control the accelerometer 3, the least significant 1 bit of the 12-bit digital output value corresponding to the frequency generated is Will change.

Therefore, the 12-bit digital output value of the accelerometer (3) is input to the 12-bit D / A converter (4), and the D / A converter (4) converts the digital output value into an analog value to the voltage controlled crystal oscillator (5). Enter it. Therefore, the voltage controlled crystal oscillator 5 is controlled, and thus the voltage controlled crystal oscillator 5 generates a clock of 1.544MHZ, which is a digital exchange transmission clock, so that the digital signal can be transmitted and at the same time, 6) and divides this input signal with a divider 6 so that the divided 8KHZ clock signal VF is inputted to the phase comparator 1 so as to form a digital phase locked loop.

As described above, the present invention omits a separate divider for dividing the input reference clock since a high frequency clock of 16.384MHZ is directly used as a reference clock to generate the transmission clock of the phase comparator 1.544MHZ. Can be easily applied to a phase locked loop whose frequency is significantly higher than that of a voltage controlled crystal oscillator or voltage controlled oscillator. Especially, since the internal clock of the digital exchanger is higher frequency than the transmit clock, It is possible to prevent signal loss and to form an economical switching network. Also, the voltage controlled crystal oscillator is controlled by changing the least significant 1 bit of the 12-bit input of the D / A converter every 125 US. To generate the clock, as well as analog The digital phase locked loop method, which does not use the reverse pass filter, eliminates the phase shift factor of the oscillation clock due to the change of the characteristics of the analog low pass filter due to environmental changes such as ambient temperature, voltage fluctuations, and humidity. Because the digital integrated circuit eliminates the difficulty of low pass filter design, the phase control due to the difference of the comparison value is slow and the phase is controlled by resetting the lowest 1 bit of the 12-bit D / A converter input. It is possible to provide an advantage of simplifying the circuit configuration by not using a calculation circuit for.

Claims (3)

In a transmission clock synchronizer of a digital exchange, a phase comparator (1) and a phase comparator (1) for comparing and counting an input reference click signal (RF) for one period of a comparison clock signal (VF) are counted. The dimension comparator 2 which judges that phase is slow and fast compared with the fixed value VS while temporarily storing, and the accelerometer 3 which adds or corrects the least significant 1 bit to the change of phase which is the output of the said dimension comparator 2 And a D / A converter 4 for converting the digital signal from the accelerometer 3 into an analog signal, and a voltage controlled crystal oscillator 5 for controlling the analog signal of the D / A converter to generate a transmission clock. And a divider 6 for dividing the transmission clock of the voltage controlled crystal oscillator 5 and outputting it to the phase comparison counter 1 as a comparison clock signal VF. Clock Synchronizer. 2. The divider 6 generates a comparison clock signal VF of 8 KHZ so that the phase reference counter 1 has an input reference clock signal RF of 16.38 MHZ. A transmission clock synchronous device of a digital exchange, characterized in that. 2. The transmission clock synchronizer device according to claim 1, wherein the voltage controlled crystal oscillator (5) is capable of generating a transmission clock of 1.544 MHZ.

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