JPS6148725B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock switching circuit for switching between a working clock and a standby clock.

In a dependent synchronization digital data network, all digital devices are controlled by a common clock and common phase synchronization signal within the network. Further, by defining the phase of the unified clock within the station between each digital device installed in the same station building, signal processing such as multiplex conversion can be performed efficiently.

In such a system, the important points are the structure of the clock distribution system and the clock receiving section.

FIG. 1 is a diagram showing the clock distribution system of a system such as that described above. In the figure, a digital clock supply device 4, which consists of a cesium atomic oscillator, a frequency divider, etc. installed at the station, divides the oscillation frequency and distributes a common clock 5 obtained to each digital device 1 and 2. . Since this clock supply device 4 simply divides and distributes one basic clock to each device 1, 2, the phase and frequency of each of these clocks are the same.
A bipolar code is used as the common clock. Transmission of signals between the digital devices 1 and 2 takes place via a data path 3.

Generally, as shown in FIG. 2, in a digital device, data is transmitted at a rising transition point of a clock pulse extracted from a received common clock, and received data is determined at a falling transition point. In such a system, data reading errors do not occur under the condition of T _D >D. Here, D=d ₃ + | d ₁ − d ₂ |, d ₁ = dl ₁ + d _Q2 , d ₂ = dl ₂ +
d _Q2 . Also, T _D is the width of the clock pulse,
d ₃ is the delay amount of the overhead cable in the data path between digital devices 1 and 2, dl ₁ and dl ₂ are the delay amount of the overhead cable in the common clock distribution path, d _Q
1 and _dQ2 are the amounts of delay in the clock receiving sections of the digital devices 1 and 2.

Generally, in the above-mentioned system, the clock distribution system is composed of two systems, a working system and a standby system, in order to increase the reliability of the system. Conventionally, such clock distribution systems use clock switching circuits that switch between working and standby clocks, but in conventional switching circuits, phase fluctuations (jitter) during switching are not absorbed by the switching circuit and are transferred to the output signal. It has the disadvantage of being visible.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock switching circuit which eliminates the above-mentioned drawbacks.

Next, the present invention will be explained in detail with reference to the drawings.

FIGS. 3 and 4 are diagrams showing a conventional clock switching circuit and waveform diagrams illustrating its operation. Incidentally, clock abnormalities include variations in the clock period due to abnormalities in the clock supply device, clock interruptions due to line interruptions for clock supply, etc., and in the following explanation, switching due to the latter clock interruption will be explained. In the figure, working and standby digital clock supplies 4 ₁ and 4 ₂
The bipolar type working clock (N system) and standby clock (E system) sent from the bipolar type converter circuits 6 and 7 are converted into unipolar signals (FIGS. 4a and 4b). The converted N-system and E-system clocks are applied to disconnection detection circuits 8 and 9, respectively. The selection circuit 10 is controlled by the disconnection detection circuits 8 and 9 and selects one of them. The clock selected by the selection circuit 10 (FIG. 4d) is input to the tuning circuit 11, and its output pulse (FIG. 4e) is given to the digital devices 1 and 2 as a common clock. This tuning circuit 11 has a function of compensating for an instantaneous interruption that occurs, for example, from the moment when the N system clock is cut off until switching to the E system by using the timing holding characteristic of this tuning circuit. Note that the above equation (1) must be satisfied at all times, including when switching the clock. However, such a switching circuit has a drawback in that phase fluctuations (jitter) during switching appear as phase jitter as shown in FIG. 4e.

Here, the phase fluctuation (jitter) during clock switching is
The occurrence of this will be explained with reference to FIG. Fourth
FIG. |dl| is a diagram illustrating the operation of the tuning circuit 11. The tuning circuit 11 is supplied with the signal shown in FIG. 4d by switching due to a clock cutoff. This tuning circuit 11 is tuned at a frequency determined by the clock pulse when the clock pulse B is normally supplied, and maintains the timing for a predetermined period even if the clock is cut off (period B). However, due to switching due to clock interruption, when pulse C is generated, waveform distortion due to pulse C occurs as shown by symbol D in Figure 4 dl, and as a result, the clock after switching (* part in Figure 4 e ), a phase fluctuation occurs over several pulses.

FIGS. 5 and 6 are a circuit diagram and an operation waveform diagram showing an embodiment of the present invention. In addition, the third
Components that are identical to those shown in the figure are given the same reference numerals.
In this embodiment, an edge-triggered trigger monostable multivibrator (abbreviated as MM) whose time constant Td is expressed by the following equation is used as the disconnection detection circuit.

t・(2n−1)<Td<t・2n …(2) where t is 1/2 period of the clock and n is an integer In a clock switching circuit with such a configuration, the time constant Td is expressed by equation (2). Since the setting is as follows, the disconnection detection signal (FIG. 6c) indicating that the N-system clock is disconnected (FIG. 6a) is output at the low level portion of the N-system clock. Therefore, the drive pulse (FIG. 6d) to the tuning circuit 11 at the moment of switching from the N system to the E system comes to be on the same time series as the N system pulse. As a result, phase fluctuations in the tuned circuit during switching can be prevented, and a high quality common clock pulse can be obtained (FIG. 6e).

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the intra-office common clock distribution system in a digital data network, FIG. 2 is a diagram showing the phase relationship between the common clock pulse and the received data signal in the data path, and FIGS. 3 and 4 a to e
1 is a diagram showing a conventional clock switching circuit and its operation waveform diagram, and FIGS. 5 and 6 a to 6e are diagrams showing an embodiment of the present invention and diagrams explaining its operation. In FIG. 5, 6, 7... bipolar/unipolar conversion circuit, 8, 9... disconnection detection circuit, 10...
... Selector, 11... Tuning circuit.

Claims (1)

[Claims] 1. A detection circuit consisting of a monostable multivibrator that detects disconnection of each of the clocks supplied from the working clock source and the backup clock source, and a selection circuit that switches between the working clock and the backup clock based on the output signal of this detection circuit. In a clock switching circuit including a clock switching circuit, the time constant Td of the detection circuit is set to
1. A clock switching circuit characterized in that the period is set to a period (n is an integer).