JPH06311075A - Automatic frequency controller in tdma satellite communication system - Google Patents

Abstract

PURPOSE:To provide an automatic frequency controller in which the frequency lock time is considerably reduced and capable of tracing even the rapid movement of a reference burst by introducing a microprocessor for the automatic frequency controller in the TDMA satellite communication system. CONSTITUTION:A microprocessor 1 reads reference burst position information BP from a resister 5 and calculates a difference from a value after a predetermined time, reads a value corresponding to the difference from a nonvolatile memory 2 to provide an output of a frequency control variable FCD. Although an oscillated frequency of a VCXO 7 is changed, since much time required for the response, the microprocessor 1 awaits the response for a predetermined time and repeats read control of the reference burst position information BP from the register 5 again. The frequency control variable is written in the nonvolatile memory 2 as a cross reference table of the frequency control variable with respect to the difference of reference burst position information (frame timing difference). An optimum frequency control variable is obtained automatically from the reference table through repetitive control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is provided for a slave station and / or a base station in a TDMA (Time Division Multiple Access) satellite communication system which is composed of at least one base station and a plurality of slave stations controlled by the base station. The present invention relates to an automatic frequency control device.

[0002]

2. Description of the Related Art In a general TDMA satellite communication system, time periodically divided on a satellite (referred to as TDMA frame) is considered, and this TDMA frame is time-divided and assigned to each earth station. The burst of its own station is transmitted so that it is within the allotted time.

In order to maintain the timing synchronization of this TDMA frame, the reference station and the slave stations are equipped with a local clock source. Generally, the reference station is provided with a high stability local clock source. The slave station receives the reference burst signal transmitted from the reference station and controls the oscillation frequency of the local clock source by using the received reference burst signal as a timing reference to achieve timing synchronization in the network. This frequency control technology is
This is one of the important technologies for MA terminal equipment.

As shown in FIG. 4, the conventional automatic frequency control device includes a reference burst detection section 20, a phase comparator 21, and
An up / down counter (U / D counter) 22,
It has a digital / analog converter (D / A converter) 23 and a voltage controlled variable frequency crystal oscillator (VCXO) 24 which operates as a local clock source.

The reference burst detection section 20 detects a reference burst signal from the received burst signal RB and outputs a reference burst detection signal BD indicating the position of the detected reference burst signal. This reference burst detection signal BD is supplied to the phase comparator 21. A local clock LC is also supplied from the VCXO 24 to the phase comparator 21, as described later. The phase comparator 21 uses the local clock LC
Referring to, an up (UP) count instruction U for increasing the U / D counter 22 based on the variation in the reception position of the reference burst signal indicated by the reference burst detection signal BD.
I or a down (DOWN) count instruction DI for down is given to the U / D counter 22. U / D counter 2
2 responds to the UP count instruction UI to count up its count value by 1, and responds to the DOWN count instruction DI to count down the count value by 1. U /
The D counter 22 sets the count value to the frequency control value FC _D.
Output as. This frequency control value FC _D is supplied to the D / A converter 23. The D / A converter 23 converts the frequency control value FC _D, which is a digital signal, into the frequency control signal FC _A , which is an analog signal. The frequency control signal FC _A is supplied to the VCXO 24. Frequency control signal F
In response to C _A , the VCXO 24 sends the local clock LC
Vary the output frequency (oscillation frequency) of.

Next, the operation of the conventional automatic frequency control device will be described. The reception burst signal RB received via the satellite is supplied to the reference burst detection unit 20, and the reference burst detection unit 20 finds the reference burst signal from the input reception burst signal RB, and when the reference burst signal is found, the reference burst signal is received. The detection signal BD is supplied to the phase comparator 21. The phase comparator 21 predicts the timing at which the reference burst detection signal BD is input on the basis of the local clock LC, and the UP count instruction UI or the DOWN count instruction D is determined depending on before and after this position.
Output I. In the U / D counter 22, the input UP
The count instruction UI or DOWN count instruction DI, counts up or counts down the count value, and outputs the count value as the frequency control value FC _D. The D / A converter 23 converts the input frequency control value FC _D into a voltage according to the value and supplies the converted voltage to the VCXO 24 as a frequency control signal FC _A to control the oscillation frequency of the VCXO 24.

On the other hand, Japanese Patent Laid-Open No. 3-70335 discloses that
It captures and holds the received frequency, measures the held received frequency, compares it with the frequency reference data that has been set, and controls the reference oscillator according to the frequency correction data corresponding to the difference frequency. A constructed "automatic frequency control device" is disclosed.

[0008]

FIG. 5 shows the time characteristic of the oscillation frequency of the VCXO 24 in the conventional automatic frequency control device shown in FIG. As shown in FIG. 5, in the conventional automatic frequency control device, over-control (too much control) and under-control (insufficient control)
It can be seen that the oscillation frequency of the VCXO 24 gradually converges while swinging up and down with respect to the reference frequency while being applied.

In the conventional automatic frequency control device, the VCXO
The frequency control spacing for 24 is a very important factor. That is, if control is added in a very short cycle,
There is a problem that the oscillation frequency of the VCXO 24 does not converge, and conversely, if the control interval is lengthened, it takes a long time until the oscillation frequency of the VCXO 24 converges.

Further, in this conventional automatic frequency control device, the control of the VCXO 24 may be erroneously performed in a system in which the position of the reference burst signal is abruptly changed, and the frequency may be difficult to converge.
That is, in a general TDMA satellite communication system, the movement of the reference burst signal is determined by the Doppler of the satellite and moves in the front-rear direction so that one cycle takes about 24 hours. However, it may be considered that the automatic frequency control device is moving in one direction in a short unit of time that causes a problem.
Therefore, even if the conventional device is used as the automatic frequency control device, once the frequency converges, the problem is not so serious.

However, SS (satellite-switched)-
In the case of the TDMA satellite communication system, the position of the reference burst signal is affected not only by the Doppler component of the satellite but also by the frequency of the clock source mounted on the satellite. Also, SS-
In the TDMA satellite communication system, the way of movement of the reference burst signal is far more complicated than in the conventional TDMA satellite communication system. This is because the reference station controls the position of its reference burst signal so as to synchronize with the timing of the satellite. As a result, in the SS-TDMA satellite communication system, when the Doppler effect is abruptly timed and the oscillation frequency of the clock source on the satellite is shifted, the reference burst signal has a fixed direction in the short term. Not only that, there is a problem that the device suddenly moves in both directions and cannot be followed up by a device using the U / D counter 22 like a conventional automatic frequency control device.

Further, the automatic frequency control device disclosed in the above-mentioned Japanese Patent Laid-Open No. 3-70335 requires a complicated circuit such as a phase locked loop as a means for capturing / holding the received frequency, and holds it. It is necessary to calculate the received frequency and compare it with frequency reference data stored in advance in the memory.

The present invention has been made to solve the above-mentioned problems, and its object is to significantly reduce the frequency pull-in time by introducing a microprocessor technique, and also to improve the characteristics of the local clock source. An object of the present invention is to provide an automatic frequency control device capable of eliminating the difference in frequency pull-in characteristic.

Another object of the present invention is to make it possible to converge the oscillation frequency (output frequency) in a TDMA satellite communication system even when the movement of the reference burst signal is rapid and the movement is not in a fixed direction. An object is to provide an automatic frequency control device.

[0015]

At least one automatic frequency control device in a TDMA satellite communication system according to the present invention is provided.
An automatic frequency control device provided in a slave station and / or a base station in a TDMA satellite communication system composed of one base station and a plurality of slave stations controlled by the base station, the output frequency being variable according to a frequency control signal. A local clock source for generating a local clock, a flywheel counter for rotating the frame position information by one frame period length based on the local clock, and a reference burst signal from the received burst signals, and the detected A reference burst detection unit that outputs a reference burst detection signal indicating the position of the reference burst signal, a latch circuit that latches frame position information with the reference burst detection signal, and outputs the latched frame position information as reference burst position information, Multiple frame timing differences and these multiple frame types A memory in which a plurality of frequency control values corresponding to the mingling difference are written, and a microprocessor for obtaining a frame timing difference for a fixed time from the reference burst position information and reading the frequency control value corresponding to the obtained frame timing difference from the memory. And a D / A converter for converting the frequency control value read by this microprocessor into a frequency control signal.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, an automatic frequency controller according to an embodiment of the present invention comprises at least one reference station (not shown) and a plurality of slave stations (not shown) controlled by the reference station. It is provided in a slave station and / or a reference station in the TDMA satellite communication system.

The illustrated automatic frequency control device includes a microprocessor 1, a non-volatile memory 2, a reference burst detection unit 3, a flywheel counter 4, a register 5, and a register 5.
It has a D / A converter 6, a voltage control type variable frequency crystal oscillator (VCXO) 7, a frequency control value calibration system 8 and a switch 9. Frequency control value calibration system 8 uses reference clock R
An oscillator 81 for generating C and a reference burst generation circuit 8 for generating a reference burst signal based on a reference clock RC.
2 and.

As will be described in detail later, this automatic frequency control device has a steady state mode (steady mode) and a frequency control value calibration mode (frequency control value calibration mode).
Operates in either mode. In the steady mode, the switch 9 selects the reception burst signal RB as shown in the figure,
In the frequency control value calibration mode, the reference burst signal output from the frequency control value calibration system 8 is selected and output.

The steady mode will be described first, and the frequency control value calibration mode will be described later.

The VCXO 7 functions as a local clock source and generates a local clock LC whose output frequency (oscillation frequency) is variable according to a frequency control signal FS _A described later. The flywheel counter 4 has a local clock LC
And the frame position information FP is output. The reference burst detection unit 3 detects the reference burst signal from the received burst signal RB and outputs the reference burst detection signal BD indicating the position of the detected reference burst signal. The register 5 stores the frame position information F
It operates as a latch circuit which latches P with the reference burst detection signal BD and outputs the latched frame position information as the reference burst position information BP. Non-volatile memory 2
In, a plurality of frame timing differences and a plurality of frequency control values corresponding to these plurality of frame timing differences are written. The microprocessor 1 obtains the frame timing difference for the fixed time T1 from the reference burst position information BP, and reads the frequency control value FC _D corresponding to the obtained frame timing difference from the non-volatile memory 2. D /
The A converter 6 converts the frequency control value FC _D read by the microprocessor 1 into a frequency control signal FC _A.

Next, the operation of the microprocessor 1 in the steady mode will be described in detail. The microprocessor 1 repeats three steps of "measurement of frequency difference", "frequency control", and "waiting for response".

In the "frequency difference measurement" step, the microprocessor 1 reads the reference burst position information BP ₀ latched in the register 5 at a certain time t ₀ ,
Wait for time T1. At time t ₁ from the time t ₀ has elapsed time T1, the microprocessor 1 reads the reference burst position information BP ₁ latched in the register 5 again.
Then, the microprocessor 1 obtains the difference between the reference burst position information BP ₀ and BP ₁ as the frame timing difference (frequency difference).

[0024] In "Frequency Control" step, the microprocessor 1 reads the frequency control value FC _D corresponding to frame timing difference obtained above from the nonvolatile memory 2, the frequency control value FC _D thus read out D / A converter 6 Output to.

In the "wait for response" step, the microprocessor 1 waits for the time T2, and repeats the above processing from the reading processing of the reference burst position information BP.

Next, the operation of the circuits other than the microprocessor 1 in the steady mode will be described.

The D / A converter 6 controls the frequency control value FC _D.
Generates a voltage corresponding to the frequency control signal FC _A. Based on this frequency control signal FC _A , the VCXO7
Oscillation frequency (output frequency) of the VCXO7 is controlled, and the VCXO7 controls the local clock LC having the controlled oscillation frequency.
Is supplied to the flywheel counter 4. The flywheel counter 4 rotates in a TDMA frame cycle (reference burst signal reception cycle), and outputs the counter value as frame position information FP.

On the other hand, the received burst signal RB received via the satellite is supplied to the reference burst detection unit 3 via the switch 9. The reference burst detection unit 3 finds the reference burst signal from the input received burst signal RB,
When the reference burst signal is found, the reference burst detection signal BD is supplied to the register 5. The register 5 latches the frame position information FP according to the reference burst detection signal BD and supplies the latched frame position information to the microprocessor 1 as the reference burst position information BP.
As described above, the microprocessor 1 reads this reference burst position information BP as necessary and executes the above-mentioned processing.

In this embodiment, the microprocessor 1 is mounted on the automatic frequency control device itself.
When a microprocessor is installed in another circuit in the TDMA terminal device, the microprocessor may perform the above-described processing.

FIG. 2 shows a state of time change of the oscillation frequency when the oscillation frequency of the VCXO 7 is controlled in the automatic frequency control device of this embodiment. As is clear from comparison with FIG. 5, the automatic frequency control device of the present embodiment does not have over-control (too much control) and under-control (insufficient control), and is quickly controlled.
It can be seen that the oscillation frequency of the VCXO7 converges.

In a general TDMA satellite communication system,
A series of control cycles of “measurement of frequency difference”, “frequency control”, and “waiting for response” may be selected as an integral multiple of the control cycle (an integral multiple of the TDMA frame cycle) for the slave station. That is, in the SS-TDMA satellite communication system described above, the position of the reference burst signal at a certain moment moves rapidly, but it hardly moves in the control cycle for the slave station described above. This is in the control of the slave station,
This is because the deviation between the satellite timing and the TDMA frame is measured, and control is applied only for the deviation.

Next, the operation in the frequency control value calibration mode will be described with reference to FIG. In this case, switch 9
Selects the reference burst signal from the frequency control value calibration system 8, and the microprocessor 1 operates in the frequency control value calibration mode.

First, a reference burst signal is input from the reference burst generator 82 instead of the reception burst signal RB (step S1). The frequency of the reference clock RC generated by the oscillator 81 is set to a desired value f _k to be measured (step S2). The microprocessor 1 substitutes the nominal value for the frequency control value N (step S3). The microprocessor 1 sets the frequency control value N in the D / A converter 6 (step S4). Microprocessor 1 has time T
Wait only 2 (step S5). The microprocessor 1 reads the reference burst position information BP (x1) from the register 5 (step S6). The microprocessor 1 waits for the time T1 (step S7). Microprocessor 1
Reads the reference burst position information BP (x2) from the register 5 (step S8). The microprocessor 1 obtains the difference (x2-x1) between the reference burst position information (step S9). The microprocessor 1 uses this difference (x2-x
It is determined whether 1) is 0 (step S10).

If the difference (x2-x1) is 0 (YES in step S10), the microprocessor 1 calculates the difference (f _k −) between the original reference frequency f _c and the frequency f _k input to the reference burst generator 82. The frequency control value for the number of symbol clocks of f _c ) is set to N and written in the nonvolatile memory 2 (step S11). Then, the process returns from step S11 to step S2.

On the other hand, if the difference (x2-x1) is not 0 (NO in step S10), the microprocessor 1 determines whether the difference (x2-x1) is positive (step S1).
2). If the difference (x2-x1) is positive (step S12)
YES), the microprocessor 1 increases the frequency control value N by 1 (step S13) and returns to step S4. On the other hand, if the difference (x2-x1) is not positive (NO in step S12), the microprocessor 1 decreases the frequency control value N by 1 (step S14), and then step S4.
Return to.

In this way, in the frequency control value calibration mode, the microprocessor 1 obtains an appropriate frequency control value for each frequency and writes it in the non-volatile memory 2.

Needless to say, the present invention is not limited to the above-described embodiments, and can be implemented with various changes without departing from the gist of the present invention. For example, a local clock source other than the voltage controlled variable frequency crystal oscillator (VCXO) may be used. Further, a memory other than the non-volatile memory may be used.

[0038]

As described above, in the automatic frequency control device of the present invention, an appropriate frequency control value according to the measured frequency difference (frame timing difference) can be directly set in the D / A converter. The frequency pull-in time can be greatly shortened. Further, the automatic frequency control device of the present invention, unlike the method of moving the U / D counter up and down at the frequency at a certain moment, integrates and measures the frequency difference for a certain period, so that the frequency jumps sharply at a certain moment. Even in such a case, frequency synchronization is possible without lowering the control sensitivity. This shows that the automatic frequency control device of the present invention is particularly effective for a system in which the jump of the reference burst signal can occur, such as the TDMA satellite communication system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an automatic frequency control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a transition of a frequency control state when the automatic frequency control device of the present invention is used.

FIG. 3 is a flowchart showing a method of a frequency control value calibration mode of the automatic frequency control device according to the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional automatic frequency control device.

FIG. 5 shows a case where a conventional automatic frequency control device is used,
It is a figure which shows the transition of a frequency control state.

[Explanation of symbols]

 1 Microprocessor 2 Non-volatile Memory 3 Reference Burst Detector 4 Flywheel Counter 5 Register 6 D / A Converter 7 Local Clock Source (VCXO) 8 Frequency Control Value Calibration System 81 Oscillator 82 Reference Burst Generator

Claims (6)

[Claims] 1. A TDM including at least one reference station and a plurality of slave stations controlled by the reference station.
In an automatic frequency control device provided in the slave station and / or the reference station in an A satellite communication system, a local clock source that generates a local clock whose output frequency is variable according to a frequency control signal, and 1 based on the local clock. A flywheel counter that outputs the frame position information around the frame cycle length, and detects the reference burst signal from the received burst signal,
A reference burst detection unit that outputs a reference burst detection signal indicating the position of the detected reference burst signal, and the frame position information is latched by the reference burst detection signal and the latched frame position information is output as reference burst position information. A latch circuit, a memory in which a plurality of frame timing differences and a plurality of frequency control values corresponding to the plurality of frame timing differences are written, and a frame timing difference for a predetermined time from the reference burst position information, Automatic frequency in a TDMA satellite communication system having a microprocessor for reading a frequency control value corresponding to the frame timing difference from the memory, and a D / A converter for converting the frequency control value read by the microprocessor into the frequency control signal. Control device. 2. The automatic frequency control device in a TDMA satellite communication system according to claim 1, wherein said local clock source is a voltage controlled frequency variable crystal oscillator. 3. The automatic frequency control device in a TDMA satellite communication system according to claim 1, wherein the memory is a non-volatile memory. 4. The microprocessor, in a steady state, a) reads reference burst position information from the latch circuit at each of the fixed time intervals, obtains the difference as the frame timing difference, and b) the frame. Read the frequency control value corresponding to the timing difference from the memory and output it to the D / A converter, and c) after outputting the frequency control value, until the local clock source responds and the output frequency stabilizes. 2. The method according to claim 1, wherein after waiting for a predetermined time, d) the steps a), b) and c) are repeated again after the lapse of the predetermined time.
Automatic frequency control device in DMA satellite communication system. 5. The automatic frequency control device in a TDMA satellite communication system according to claim 4, wherein the series of control cycles of steps a) to c) is an integral multiple of a TDMA frame cycle. 6. The automatic frequency control device includes an oscillator that generates a reference clock and a reference burst generation device that generates a reference burst signal based on the reference clock, and the reference frequency is adjusted when the frequency control value is calibrated. A burst generator is connected to the reference burst detection unit to put the microprocessor in a frequency control value calibration mode, and the microprocessor: a) optimizes each frequency by changing the frequency of the reference clock of the oscillator. 2. The automatic frequency control device in the TDMA satellite communication system according to claim 1, wherein: b) the optimum frequency control value thus found is written and held in the memory.