JPH0126596B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a color television synchronization signal that generates a pulse signal (second synchronization signal) synchronized with a subcarrier signal in an input color television signal and other synchronization signals such as a horizontal synchronization signal. Regarding the generator.

A signal obtained by time-division multiplexing a plurality of signals, a television signal, etc. usually contains a plurality of types of synchronization signals.
When performing digital processing on such signals, a sampling clock signal, etc. (second synchronization signal) whose phase is synchronized with the plurality of synchronization signals described above is created, and various control pulses are further processed using the sampling clock signal as a reference. A synchronization signal generator is required to generate the following. For example, a color television signal includes four types of synchronization signals: a vertical synchronization signal, a horizontal synchronization signal, a frame synchronization signal, and a subcarrier signal. When input signals are digitally processed, a clock is created that is phase-synchronized with the subcarrier and also, for example, with a horizontal synchronization signal, and this clock is used as a reference for various control signals and second synchronization signals. It is necessary to generate a signal.

Conventionally, in order to generate the above-mentioned second synchronization signal, the second synchronization signal is generally generated by counting a clock whose phase is synchronized with the subcarrier signal using a counter. By resetting the second synchronization signal to the horizontal synchronization signal, the second synchronization signal is also synchronized with the horizontal synchronization signal. However, the horizontal synchronization signal extracted from the input television signal is accompanied by phase jitter due to distortion of the input synchronization signal waveform. This jitter spans several samples of the basic clock and therefore causes jitter at the time of resetting the counter, causing the period of the synchronization signal generator output to fluctuate. Digital processing of television signals requires that the number of clocks within the horizontal scanning period be constant.
Using the conventional synchronization signal generators described above is disadvantageous.

The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
To generate a stable second synchronization signal that is synchronized with a subcarrier of an input color television signal and another synchronization signal (for example, a horizontal synchronization signal), and which does not cause phase fluctuations due to some jitter in the input synchronization signal. An object of the present invention is to provide a synchronization signal generation circuit for television signals that can perform the following functions.

The synchronization signal generation circuit of the present invention receives a subcarrier signal of an input color television signal and a long period synchronization signal synchronized with the subcarrier signal, and generates a second synchronization signal whose phase is synchronized with the subcarrier signal and the input synchronization signal. In a television signal synchronization signal generator that generates a signal, a counter that divides the frequency of the subcarrier;
a synchronization signal generation circuit that generates the second synchronization signal in phase synchronization with the output of the counter; a phase difference circuit that takes a phase difference between the output of the counter and the input synchronization signal; and an output of the phase difference circuit. a first phase difference determination circuit that synchronizes the second synchronization signal output from the synchronization signal generation circuit with the input synchronization signal by resetting the counter when the second synchronization signal exceeds a first phase difference reference; and a second phase difference determination circuit that resets the frequency dividing circuit when a second phase difference reference, which is wider than the first phase difference reference, is exceeded, and an output of the phase difference circuit at the time of initial setting. is inputted into the first phase difference determination circuit, and the number of times that the output of the first phase difference determination circuit is within the first phase difference reference is counted, and the output of the phase difference circuit is input to the first phase difference determination circuit for a certain number of times or more. and a switching control circuit that switches the output of the phase difference circuit to the second phase difference determination circuit and inputs the output if the phase difference is within the phase difference reference.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. That is, the color television subcarrier is inputted from the input terminal 1, and the frequency is divided by 1/455 by the counter 2. The output of the counter 2 is input to a phase lock loop 3 to generate a clock phase-synchronized with the subcarrier signal, and the clock is supplied to a pulse generation circuit 4. The pulse generating circuit 4 is composed of a logic circuit such as a PROM, and is a circuit that receives each count output of the phase lock loop 3 and generates various pulses necessary for various controls. The phase lock loop 3 includes a phase difference circuit 31, a voltage controlled oscillator 32, and a local counter 33. The phase difference circuit 31 controls the oscillation frequency of the voltage controlled oscillator 32 based on the phase difference between the frequency-divided output signal of the counter 2 and the output signal of the local counter 33, and outputs the output of the voltage controlled oscillator 32 to the local counter 3.
By dividing the frequency by 3 and inputting it to the phase difference circuit 31, a phase lock loop is formed.

On the other hand, a horizontal synchronizing signal is input to the phase difference circuit 5 from the input terminal 8 . The phase difference circuit 5 divides the input signal into a signal having the same period as the output of the counter 2 by dividing the input signal by two using the frequency divider 51, and calculates the phase difference between the output of the frequency divider 51 and the output of the counter 2. Phase difference circuit 52
Take it by. The output of the phase difference circuit 5 is input to the control circuit 6 and enters either the first phase difference determination circuit 61 or the second phase difference determination circuit 62 via the switch 65. The first and second phase difference determination circuits 61 and 62 each have a first phase difference reference H,
The output of the phase difference circuit 52 is determined based on the second phase difference reference K (>H), and when the output exceeds the reference value, the counter 2 is reset. Initially, the switch 65 is connected to the first phase difference determination circuit 61 side as shown by the solid line in the figure, and the output of the phase difference circuit 52 is determined by the first phase difference reference H. When it is larger, the counter 2 is reset to bring the output phase of the counter 2 into phase synchronization with the input horizontal synchronizing signal. As a result, the phase lock loop 3 is phase-locked with the subcarrier and the input horizontal synchronization signal.
The counter 63 counts the number of times the phase difference determination circuit 61 determines that the phase difference is smaller than the first reference H, and the switching control circuit 64 switches the switch 65 when the counted value reaches a certain value. Thereafter, the second phase determination circuit 62 performs phase determination. That is, the second
The phase is determined based on the phase difference reference K. The second phase difference reference K has a wider width than the first phase difference reference H, so that even if the output of the phase difference circuit 52 temporarily fluctuates somewhat due to phase jitter of the input horizontal synchronizing signal, etc. , the phase difference determination circuit 62 does not reset the counter 2. Therefore, a stable second synchronization signal without phase fluctuation can be obtained from the synchronization signal generation circuit comprising the phase lock loop 3, the pulse generation circuit 4, and the like. However, if the phase difference exceeds the second phase difference reference, the counter 2 is reset by the output of the second phase difference determination circuit 62, and synchronization is re-established using the first phase difference reference. It turns out.

FIG. 2 is a time chart showing the signals of each part of the above embodiment. FIG. 2A shows the output of the counter 2, FIG. 2B shows the output of the counter 51, and FIG. 2C shows the output of the phase difference circuit 52. Note that d and e in the same figure show reference widths when the first phase difference reference H is one clock width and the second phase difference reference K is three clock widths. This shows that the counter 2 is reset when the signal shown in figure c exceeds this reference width.

As described above, in the present invention, two types of phase difference standards are provided, wide and narrow, and the narrow phase difference standard is used at the start of retraction, and the phase point with the highest probability (if there is a phase fluctuation, the center point) After the control is stabilized, the phase difference is switched to a wide phase difference reference. Therefore, even if some phase jitter occurs in the input synchronization phase after the pull-in is completed, as long as the average value does not change,
A stable second synchronization signal without phase fluctuation is intermittently output from the synchronization signal generator. That is,
A stable second synchronization signal with a constant period can always be supplied without unnecessary resets being applied to the synchronization signal generator. This second synchronization signal is phase-locked to the center of the phase fluctuation of the input synchronization signal, and the phase of the output signal is not biased to one side.
Therefore, there is an advantage that digital processing of an input color television signal can always be performed at the correct phase position with respect to the input signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 shows the signals of each part of the above embodiment and the first and second signals.
This is a time chart showing the phase difference reference width of . In the figure, 1, 8...Input terminal, 2...Counter, 3...Phase lock loop, 4...Pulse generation circuit, 5...Phase difference circuit, 6...Control circuit, 5
1... Frequency divider circuit, 52... Phase difference circuit, 61...
1st phase difference determination circuit, 62...2nd phase difference determination circuit, 63...counter, 64...switching control circuit, 65...switching device.

Claims (1)

[Claims] 1 A television signal synchronization device that receives a subcarrier signal of an input color television signal and a long-period synchronization signal synchronized with the subcarrier signal and generates a second synchronization signal phase-synchronized with the subcarrier signal and the input synchronization signal. The signal generator includes: a counter that divides the frequency of the subcarrier; a synchronization signal generation circuit that generates the second synchronization signal in phase synchronization with the output of the counter; A phase difference circuit that takes a phase difference; and a second synchronization signal output from the synchronization signal generation circuit by resetting the counter when the output of the phase difference circuit exceeds a first phase difference reference. a first phase difference determination circuit that performs phase synchronization with the input synchronization signal;
a second phase difference determination circuit that resets the frequency dividing circuit when a second phase difference reference, which is wider than the first phase difference reference, is exceeded; input into a first phase difference determination circuit, count the number of times that the output of the first phase difference determination circuit is within the first phase difference reference, and count the number of times that the output of the first phase difference determination circuit is within the first phase difference reference, and the output of the phase difference circuit is A synchronizing signal generator for television signals, comprising: a switching control circuit that switches the output of the phase circuit to the second phase difference determining circuit and inputs the output if the phase difference is within a reference phase difference.