JPS60232786A - Synchronizing pulse generating circuit in special effect waveform generator - Google Patents

Abstract

PURPOSE:To change easily a synchronizing pulse to a different TV type by combining horizontal and vertical synchronizing counters with horizontal and vertical memory circuits and obtaining various synchronizing pulses necessary in a specific effect waveform generator. CONSTITUTION:The horizontal and vertical synchronizing memory circuits 29, 30 of which contents can be changed can send plural synchronizing pulses to generate a specific effect waveform. A clock signal from a PLL circuit consisting of a phase comparator 25 and a voltage control oscillator 26 is multiplied by the integer times of the horizontal synchronizing on the basis of an input synchronizing signal from a terminal 21 and a horizontal synchronizing signal from the circuit 29 and a clock signal synchronized with the input signal is outputted. Receiving the clock signal and the output signal from the circuit 29, the horizontal synchronizing counter 27 an output signal consisting of plural bits to the circuit 29. Receiving the vertical component of the input synchronizing signal and the signal from the circuit 29, the vertical synchronizing counter 28 sends an output consisting of plural bits to the circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a synchronization pulse generation circuit in a special effect waveform generator.

(2) Description of the Prior Art Since the vertical frequency, number of scanning lines, etc. differ depending on the television system, it is necessary to adjust the synchronization system of the equipment used accordingly. Traditionally, when television systems are different,
It was necessary to modify the equipment for each method.

While some analog special effects waveform generators were relatively easy to change, it was not so easy to make changes to all digital special effects waveform generators.

An example of a rough clock diagram of the special effects waveform generator is shown in FIG. The effect waveform is produced by synthesizing and shaping signals such as sawtooth waves from the horizontal periodic fundamental wave generator 8 and the vertical periodic fundamental wave generator 4 in the waveform shaping circuit 5 and outputting the resultant signal via the blanking gate circuit 6. . Various synchronization pulses are required to generate and process these internal signals. 1 is a synchronizing signal input terminal, and 7 is an output terminal. If the television system is different, it is necessary to change the synchronization pulse generation circuit 2. In the case of a digital type, it is not easy to change the number of scanning lines, blanking period, etc.

Also, the blanking used in the special effect waveform generator uses a narrow blanking period, which is slightly different from the standard value. Additionally, as the number of waveform patterns increases, different timing pulses may be required, and these pulses may also need to be changed.

(3) Detailed Description of the Invention The present invention provides a horizontal period counter, a vertical period counter,
Horizontal periodic memory circuit, vertical periodic memory circuit, PLL
The present invention provides a synchronization pulse generation circuit in a special effects waveform generator, which is equipped with a circuit and which allows the television system to be easily changed by changing the contents of the two memory circuits.

(4) Structure of the Invention The present invention provides a horizontal periodic memory circuit and a vertical periodic memory circuit whose memory contents can be changed, which send out a plurality of periodic pulses used to generate special effect waveforms, and an input synchronizing signal and a horizontal periodic memory circuit. a PLL circuit that receives a horizontal synchronization signal from a memory circuit, multiplies it by an integral multiple of the horizontal period, and outputs a clock signal synchronized with the input synchronization signal; a horizontal period counter that receives a horizontal period signal and sends a multi-bit output signal to the horizontal period memory circuit; and a horizontal period counter that receives a vertical component of the input synchronization signal and a signal from the horizontal period memory circuit and outputs a multi-bit output signal. A synchronous pulse generation circuit in a special effects waveform generator, characterized in that it has a vertical period counter that sends a signal to the vertical period memory circuit.

(5) Examples An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the synchronous pulse generation circuit of the special effect waveform generator according to the present invention includes a horizontal period counter 27,
vertical period counter 28 and the two counters 27
．． A horizontal periodic memory circuit 29 and a vertical periodic memory circuit 30, whose memory contents can be changed, receive signals from the horizontal periodic memory circuit 28 and generate various synchronizing pulses, and the horizontal periodic memory circuit 29 is separated from the signals and the composite synchronizing signal from the outside. It is composed of PLL circuits 25 and 26 that receive a horizontal periodic component signal and perform phase-synchronized oscillation.

Further, the vertical component of the composite synchronization signal from the outside is supplied to the vertical counter circuit 28, and the counter is set to a constant value for each vertical period. The vertical period counter 28
For example, the number of bits is such that the necessary counting can be performed even when the number of scanning lines is 625. Therefore, if a pulse with a period of % of the horizontal period is used as the counter clock, the number of bits of the counter is 9 bits. Further, 34 is an output terminal (group) of the horizontal periodic memory circuit 29.
, 35 are phase control terminals of the horizontal period memory circuit 29.

The composite synchronization signal supplied to the synchronization signal input terminal 21 is supplied to a vertical pulse separation circuit 22 and a horizontal synchronization pulse separation circuit 23, where it is separated into vertical and horizontal frequency components. This separated vertical frequency component signal controls a vertical period counter 28. On the other hand, the horizontal frequency component signal passes through the phase adjustment circuit 24 and becomes one input signal of the phase comparison circuit 25. Another input signal to the phase comparator circuit 25 is supplied from the horizontal period memory circuit. Phase comparison circuit 25 and V
CO26 is a so-called phase-locked loop (PLL).
circuit). An output obtained by multiplying the horizontal period pulse is obtained from the output of the VCO 26, and this signal is used as a clock signal for the horizontal period counter 27.

The horizontal period counter 27 counts clocks, generates multiple bits of parallel data, and drives the horizontal period memory circuit 29. One output of the horizontal period memory circuit 29 is designed to generate a pulse when the input reaches data of 909, for example, and this pulse resets the horizontal period counter 27 and serves as an input signal to the phase comparator circuit 25. . In this way, the counter will be θ~90
You will be counting between 9. The vertical period counter 28 counts a signal from the horizontal period memory circuit 29, for example, a pulse of % of the horizontal period as a clock, is reset by a signal from the vertical pulse separation circuit 22, and outputs data of, for example, θ to 524. The vertical period memory circuit 30 receives the signal from the vertical period counter 28 and generates various pulses required within the special effects waveform generator. If a composite blanking signal is required, the horizontal and vertical components are sent from the combining circuit 31 to the blanking output terminal 83.

If various waveforms are still generated digitally, the processing time of the waveform shaping circuit 5 in FIG. 2 may differ.

For example, one board is sufficient for up to a certain number of waveforms, but in order to increase the number of waveforms, if another board is added in series, the output signal from the synchronous pulse generation circuit 2 in Fig. 2 may be It is necessary to change the phase. The phase control terminal 35 in FIG. 1 is provided to change the horizontal periodic pulse phase as required.

When changing the number of scanning lines, vertical frequency, blanking period, etc. depending on the television system, the system is changed by replacing the read-only memories used in the horizontal pulse memory circuit 29 and the vertical period memory circuit 30. Furthermore, the phases of the various synchronization pulses sent out from the output terminals 32 and 33 can be easily changed by replacing the read-only memory.

Note that in the horizontal period memory circuit 29 and the vertical period memory circuit 30, a register is provided between the signal from the lead-on memory and the output in order to match the timing of the output pulse. In this case, a clock signal is required to drive the register, but the horizontal period counter 2
7 and the clock supplied to the vertical period counter 28 can be used.

Blanking used in special effects waveform generators generally involves narrowing the horizontal blanking period, but it is clear that this can be set in the memory of the horizontal period memory circuit 29 of FIG.

(6) Detailed description of the invention As explained above, the present invention comprises two counter circuits and two counter circuits.
Since the various synchronization pulses required inside the special effects waveform generator are obtained by combining two memory circuits, it is possible to easily change to a different television system by simply changing the contents of the memory circuit. This has the effect of making it possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a synchronization pulse generation circuit according to the present invention, and FIG. 2 is a block diagram showing the configuration of a special effect waveform generator. l... Synchronous signal input terminal, 2... Synchronous pulse generation circuit, 3... Horizontal period fundamental wave generator, 4... Vertical period fundamental wave generator, 5... Waveform shaping circuit, 6... Block Ranking gate circuit, 7... Output terminal, 21... Synchronous signal input terminal, 22... Vertical pulse separation circuit, 23... Horizontal periodic pulse separation circuit, 24... Phase adjustment circuit, 25...
・Phase comparison circuit, 26...VCO, 27...Horizontal period counter, 28...Vertical period counter, 29.
...Horizontal pulse memory circuit, 30...Vertical pulse memory circuit, 81...Composition circuit, 32...Output terminal (
3B--Blanking output terminal, 34--Output terminal (group), 35--Phase control terminal.

Claims (1)

[Claims] (1) A horizontal periodic memory circuit and a vertical periodic memory circuit whose memory contents can be changed, which send out multiple periodic pulses used to generate special effect waveforms, and an input synchronization signal and horizontal synchronization from the horizontal periodic memory circuit. a PLL circuit that receives a signal and outputs a clock signal that is multiplied by an integral multiple of the horizontal period and is synchronized with the input synchronization signal;
a horizontal period degree counter that receives a clock signal from the LL circuit and a horizontal period signal from the horizontal period memory circuit and sends a multi-bit output signal to the horizontal period memory circuit; 1. A synchronous pulse generation circuit in a special effect waveform generator, comprising a vertical period counter that receives a signal from a horizontal period memory circuit and sends a multi-bit output signal to the vertical period memory circuit.