JP2517443B2 - TV camera synchronization circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a synchronizing circuit for synchronizing the operation of a television camera and the operation of a television monitor by using a composite signal including various synchronizing signals.

(B) Conventional technology When configuring an imaging system using multiple TV cameras, such as a surveillance system using surveillance cameras, the operations of each television camera must be synchronized so that multiple videos can be processed simultaneously. Is desired. Normally, the operation of each TV camera is set based on the reference clock from the oscillation source built into each TV camera, and each TV camera has its own operation timing unless the operation timing is particularly matched. It will operate at the timing. Therefore, generally, the operation of each television camera is synchronized by giving a common synchronization signal to each television camera.

FIG. 5 is a waveform diagram of the composite signal CSY for obtaining the operation timing of the television camera, showing the case of the NTSC system.

The composite signal CSY is externally input to the television camera and includes a horizontal synchronizing signal HSY, a vertical synchronizing signal VSY and an equivalent pulse EQP. These horizontal sync signals HS
The Y, vertical synchronizing signal VSY, and equivalent pulse EQP are arranged in time series in a predetermined order, and the horizontal synchronizing signal HSY and the vertical synchronizing signal VSY are separated by the differentiating circuit and the integrating circuit.
That is, the horizontal sync signal HSY is obtained by differentiating the composite signal CSY and detecting the fall, and the composite signal CSY is integrated, and the vertical sync signal VSY is obtained from the change in the integrated value.

Figure 6 shows the composite signal CSY to the horizontal sync signal HSY.
5 is a block diagram showing a configuration of a synchronization circuit that obtains a vertical synchronization signal VSY.

The mixed signal HYB input from the outside is separated into the video signal VDO and the composite signal CSY in the sync signal separation circuit (1), and the composite signal CSY is further input to the vertical / horizontal separation circuit (2). . In the vertical / horizontal separation circuit (2), the composite signal CSY is differentiated to detect the falling edge to obtain the horizontal sync signal HSY ₀ , and the composite signal CSY is integrated to change the integrated value from the vertical sync signal VSY.
You are getting SY.

On the other hand, the voltage controlled oscillator (VCO) (3) generates the reference clock MCK according to the output PDO of the phase comparator (4) described later and counts the counter (5). The vertical synchronizing signal VSY is supplied to the counter (5) as a reset signal RES, and the counter output is supplied to the decoder (6). The decoder (6) creates a horizontal synchronization signal HSY ₁ from the counter output of the counter (5) and, together with the horizontal synchronization signal HSY ₀ from the vertical / horizontal separation circuit (2), a phase comparator (4).
Is input to The phase comparator (4) uses the horizontal synchronization signal HSY ₀
And the phase of the horizontal sync signal HSY ₁ is compared, and the comparison output PDO is supplied to VCO (1) and PLL (Phase Locked Loo
p). Therefore, the horizontal synchronizing signal HSY ₁ is synchronized with the horizontal synchronizing signal HSY ₀ separated from the composite signal CSY.

(C) Problems to be Solved by the Invention However, according to the above-mentioned synchronizing circuit, the horizontal synchronizing signal HSY and the vertical synchronizing signal are separated from the composite signal CSY.
Since analog circuits such as differentiating circuits and integrating circuits are mainly used when obtaining VSY, it is necessary to fully consider the delay of these analog circuits. The amount of delay in such an analog circuit has temperature dependency, and it is extremely difficult to determine each parameter of the analog circuit while sufficiently considering the amount of delay.

Furthermore, if the VCO (1) oscillation range is narrow, the PLL
Until the lock occurs, that is, the time until the horizontal synchronizing signal HSY ₁ synchronizes with the horizontal synchronizing signal HSY ₀ becomes long, and the rise of the device is delayed.

Therefore, the present invention, without using an analog circuit,
The object is to stably separate the horizontal synchronizing signal HSY and the vertical synchronizing signal VSY, shorten the rise time of the device, and easily synchronize the operation of the television camera with the composite signal CSY.

(D) Means for Solving the Problems The present invention has been made to solve the above problems, and is characterized in that a television camera equipped with an image pickup device that is scanned in horizontal and vertical directions. In the synchronizing circuit of the television camera, which synchronizes the operation of the television camera with a predetermined timing by giving a composite signal including a horizontal synchronizing signal and a vertical synchronizing component, a coefficient circuit which counts a constant period clock and operates in the horizontal scanning period. , A signal of a plurality of horizontal scanning periods having different phases is obtained from the output of the coefficient circuit, and the signals are combined to generate a time division signal having a number of clock pulses corresponding to the number of phases of the signal in one horizontal scanning period. Decoding circuit that occurs, detection circuit that detects the fall or rise of the composite signal, start according to the detection output of this detection circuit A horizontal sync separation circuit that performs a half killer operation on the detection output while counting a suitable number of clock pulses of the split signal to remove a signal shorter than the horizontal scanning period to obtain horizontal scanning timing, the falling edge of the composite signal Alternatively, it is provided with a vertical sync separation circuit that detects a change before and after rising to obtain a vertical scanning timing.

(E) Operation According to the present invention, the horizontal scanning period is divided into a plurality of periods by the time division signal that generates a plurality of clock pulses in the horizontal scanning period, and an appropriate number of divisions are performed from the falling or rising timing of the composite signal. The period of the half killer operation is set over the period. Therefore, an equivalent pulse having a period shorter than the horizontal scanning period is removed to obtain a horizontal synchronizing signal. By synchronizing this horizontal synchronizing signal with one signal of the horizontal scanning period of the decoding circuit, the operation of the television camera is converted into a composite signal. Synchronize.

(F) Embodiment An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the synchronizing circuit of the present invention.

The fall detection circuit (10) detects the fall of the composite signal CSY based on the basic clock MCK, and outputs a detection signal CSY ₁ according to the basic clock MCK. This detection signal CSY ₁ is used as a reset signal for the counter (11) that counts the basic clock MCK, and operates the counter (11) in the horizontal scanning cycle to generate a composite signal.
Synchronize to CSY. Decoder (12), counter (11)
Is configured to obtain an output at a predetermined value, and a detection signal CSY ₂ and a latch pulse delayed by a certain period with respect to the falling edge of the composite signal CSY, a half killer pulse generation circuit (described later) ( 14) and the latch circuit (13). This detection signal CSY ₂ is the detection signal
A delay of about 1/10 of the horizontal scanning period is given to CSY ₁ , and the start timing of the half killer pulse generation circuit (14) is determined. The latch circuit (13) separates the vertical sync signal VSY from the composite signal CSY.
The falling edge of the vertical synchronizing signal VSY is detected by latching the composite signal CSY at a timing delayed for a certain period from the falling edge of the composite signal CSY.

The counter (17), which counts according to the output of the VCO (16), is reset by the horizontal synchronizing signal HSY and starts counting, and gives its output to the decoder (18). The decoder (18) decodes the output of the counter (17) to output horizontal synchronization signals HSY _{1 to} HSY ₄ having mutually different phases. These phase differences are set to be substantially equal to each other, and are combined by the NAND gate (19) to make the horizontal scanning period 4 times.
A time division clock CLK for division is created.

The half killer pulse generator (14) detects the detection signal CSY ₂
According to the clock pulse of the time-division clock CLK, a half killer pulse KLR for performing a half killer operation is generated during a predetermined period. That is, half killer pulse KLR
After the rise timing of the detection signal CSY _2, at the rising edge of the time-division clock CLK rises at the rise timing of the next time division clock CLK, the clock pulse of the time division clock CLK after receiving a predetermined number It is set to fall. Then, the half killer pulse KLR and the detection signal CSY ₁ are combined by the OR gate (20), whereby the half killer operation is performed on the detection signal CSY ₁ . Therefore, the signal having a cycle shorter than the horizontal scanning cycle, that is, the equivalent pulse EQP is removed from the detection signal CSY ₁ to obtain the horizontal synchronizing signal HSY.

Horizontal sync signal HSY separated from composite signal CSY
Is compared in phase with the horizontal synchronization signal HSY ₁ output from the decoder (18) in the phase comparison circuit (15), and the comparison output is VC
It is given to O (16) to configure the PLL. Thus, operation of the counter (17), i.e., the horizontal sync signal HSY ₁ ~HSY ₄ is synchronized to the composite signal CSY.

FIG. 2 is a diagram showing the configuration of the fall detection circuit (10).

The flip-flop (26) receives the composite signal CSY at its D input, and Q at the timing according to the basic clock MCK.
The output is given to the D input of the flip-flop (27). The flip-flop (27) ORs the timing output according to the inverted signal of the basic clock MCK together with the composite signal CSY.
Fill in the gate (28). Then, the detection signal CSY ₁ is output from the OR gate (28). Therefore, the composite signal
When CSY falls, the OR gate (28) is inverted and detection signal C
SY ₁ falls, the Q output of the flip-flop (26) rises at the next rise of the basic clock MCK, and the flip-flop (2
When the output of 7) rises, the OR gate (28) is inverted and the detection signal CSY ₁ rises.

FIG. 3 is a diagram showing an example of the half killer pulse generation circuit (14) and shows a case where the time division clock CLK divides the horizontal scanning period into four.

The flip-flop (21) is supplied with the power supply potential at the D input and supplies the Q output to the flip-flop (22) in accordance with the detection signal CSY ₂ . The flip-flop (22) supplies the Q output to the first-stage D input and the OR gate (25) of the two-stage flip-flops (23) (24) connected in series according to the time division clock CLK. Also, these flip-flops (2
3) (24) shifts the Q output of the flip-flop (22) according to the time division clock CLK,
The output of 4) is given to the OR gate (25). Therefore, when the detection signal CSY ₂ rises, the half killer pulse KLR rises at the next rise of the time division clock CLK, and the half killer pulse KLR falls at the next third rise.

The half killer pulse generation circuit (14) may be configured by using a counter with an appropriate number of bits that counts with the time division clock CLK.

 Next, the half killer operation will be described.

FIG. 4 is a timing chart for explaining the half killer operation, and shows the case of the four-layer structure according to FIG.

4 horizontal synchronizing signal phase HSY ₁ ~HSY ₄ are specifically produced by the decoder (18) for decoding the output of the counter (17) has a substantially equal phase difference to each other. For example, NT
In the SC method, the counter (17) is 90 during the horizontal scanning period.
Decoders for counting eight clocks (18)
Are configured to obtain outputs when the output of the counter (17) is 0, 227, 454 and 681. Then, the time division clock CLK synthesized by the NAND gate (19) generates four clock pulses in the horizontal scanning period to divide the horizontal scanning period into four.

Detection signal CSY _{2 which is} delayed for a certain period from detection signal CSY ₁
When the Q output of the flip-flop (21) rises at the rising edge of, the D input of the flip-flop (22) becomes the power supply potential, and the Q output of the flip-flop (22) rises at the next rising edge of the time division clock CLK. Therefore, the next time division clock after the detection signal CSY ₂ rises.
Half-killer pulse KLR rises at the rising edge of CLK.

Then, at the second rise of the time division clock CLK, the Q output of the flip-flop (23) rises, and the following 3
When the output of the flip-flop (24) falls at the rising edge of the time division clock CLK for the eighth time, the OR gate (25) is inverted and the half killer pulse KLR falls. Therefore,
The half killer pulse KLR sets the half killer operation period to two clock periods of the time division clock CLK when the detection signal CSY ₂ rises.

So, this killer killer pulse KLR and detection signal CSY ₁
Therefore, the equivalent pulse EQP having a shorter cycle than the horizontal synchronizing signal HSY is removed, and the horizontal synchronizing signal HSY ₀ is obtained. Then, the horizontal synchronizing signal HSY ₀ and the horizontal synchronizing signal HSY ₁
~ Phase comparison with one of HSY ₄ and control VCO (16) that composes PLL to synchronize with composite signal CSY.

Here, the reason why the detection signal CSY ₂ delayed from the composite signal CSY is used to determine the start timing of the half killer pulse generation circuit (14) is to prevent the half killer operation from malfunctioning. Horizontal sync signal
HSY ₁ ~HSY ₄ is to compensate for the error in the period until the synchronization with the composite signal CSY. For example, the horizontal sync signal HSY ₁ ~
When the period of HSY ₄ is shorter than the original horizontal scanning period, the detection signal when the CSY ₁ rise have been inputted immediately before the fall of the time division clock CLK, the half killer pulse KLR before the detection signal CSY ₁ falls Therefore, there is a possibility that the equivalent pulse EQP cannot be erased, and therefore the start timing of the half killer operation is set in advance according to the detection signal CSY ₂ which is delayed with respect to the composite signal CSY.

That is, if the start timing of the half killer operation is set at a timing delayed with respect to the composite signal CSY,
When the falling edge of the detection signal CSY ₁ is input immediately before the falling edge of the time division clock CLK, the start timing of the half killer operation is delayed by one clock of the time division clock CLK, so the half killer pulse KLR is detected by the detection signal CSY.
It will never fall before ₁ .

In this way, the detection signal CSY ₂ delayed with respect to the composite signal CSY is used to determine the start timing of the half killer operation when the horizontal synchronization signal HSY _n is in the 4 to 5 phase, and in the configuration of 6 phases or more. In this case, the detection signal CSY ₁ may be used for setting the start timing of the half killer operation without delay.

(G) Effect of the Invention According to the present invention, a half-killer operation can be performed with a simple circuit configuration to separate a horizontal synchronizing signal from a composite signal, and stable operation can be expected.

In addition, if the half killer pulse is latched at each timing of the vertical synchronizing signal, the field identification signal that is inverted for each field can be obtained, which speeds up the field recognition and allows each circuit to synchronize with the composite signal in a short time. Rises faster.

[Brief description of drawings]

FIG. 1 is a block diagram showing a synchronizing circuit of the present invention, FIG. 2 is a diagram showing a configuration of a fall detection circuit, FIG. 3 is a diagram showing a configuration of a half killer pulse generation circuit, and FIG. 4 is a half killer operation. FIG. 5 is a waveform diagram of a composite signal, and FIG. 6 is a block diagram showing a conventional synchronizing circuit. (1) …… Synchronous signal separation circuit, (2) …… Horizontal / vertical separation circuit, (3) (16) …… VCO, (4) (15) …… Phase comparison circuit, (5) (11) ( 17) …… Counter, (6)
(12) (18) …… Decoder, (10) …… Falling detection circuit, (14) …… Half-killer pulse generation circuit, (19)
...... NAND gate, (20) …… OR gate, (21) to (24)
(26) (27) …… Flip-flop.

Claims (3)

(57) [Claims] 1. A television camera in which a composite signal including horizontal synchronization and vertical synchronization components is applied to a television camera equipped with an image pickup device for scanning in the horizontal and vertical directions to synchronize the operation of the television camera at a predetermined timing. A coefficient circuit that operates in a horizontal scanning cycle by counting a fixed number of basic clocks in a synchronizing circuit. A plurality of horizontal scanning cycle signals with different phases are obtained from the output of this coefficient circuit, and the signals are combined. Circuit for generating a time division signal having a number of clock pulses corresponding to the number of signal phases in one horizontal scanning period, a detection circuit for detecting the fall or rise of the composite signal, and activation according to the detection output of this detection circuit Then, while counting an appropriate number of clock pulses of the time division signal, a half killer operation is performed for the detection output. A horizontal sync separation circuit that obtains horizontal scan timing by removing signals shorter than the horizontal scan cycle; and a vertical sync separation circuit that obtains vertical scan timing by detecting changes before and after the fall or rise of the composite signal. This is a synchronizing circuit for TV cameras. 2. The decoding circuit by comparing the phase of the horizontal synchronizing signal separated from the composite signal with one signal of the horizontal scanning cycle of the decoding circuit and adjusting the cycle of the basic clock according to the phase difference. 2. The synchronizing circuit for a television camera according to claim 1, wherein the operation of is synchronized with the composite signal. 3. A detection output of the detection circuit is delayed by a period shorter than a horizontal scanning cycle, and a start timing of a half killer operation of the horizontal sync separation circuit is set according to the delayed detection output. A synchronizing circuit for a television camera according to claim 1.