JPH03758Y2 - - Google Patents

Description

[Detailed Description of the Invention] Purpose of the Invention Industrial Application Field The present invention relates to a digital variable frequency circuit used in fields such as digital communication and information processing.

Conventional technology Conventionally, in the fields of digital communication and information processing, in order to vary the oscillation frequency of a digital signal,
A voltage controlled oscillator (VOC) is used.

Problems to be Solved by the Invention With the conventional digital variable frequency circuit using a VCO described above, it is difficult to realize a variable range as large as an octave.

Means for Solving the Constituent Problems of the Invention The digital variable frequency circuit of the present invention, which solves the problems of the prior art described above, has three frequency dividing circuits and two frequency dividing circuits.
It is constructed to realize a variable frequency range as wide as an octave using a simple circuit consisting of two flip-flops and two exclusive OR circuits.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a circuit diagram showing the configuration of a digital variable frequency circuit according to an embodiment of the present invention.

In the figure, 1 is an input terminal that receives the clock signal CK.
2 is an input terminal that receives the frequency selection signal SEL, 3 is a frequency divider circuit that divides the clock signal CK supplied to input terminal 1 by 3, and 4 is also the clock signal CK.
This is a divide-by-2 circuit that divides the frequency by two.

5 is a flip-flop that holds the frequency selection signal SEL in synchronization with the clock signal CK; 6 is an exclusive OR circuit that outputs the exclusive OR of the output of the flip-flop 5 and the clock signal CK; 7 is an exclusive OR circuit that outputs the exclusive OR of the output of the flip-flop 5 and the clock signal CK; This is a flip-flop that holds the output of the frequency divider circuit 3 in synchronization with the output of the exclusive OR circuit 6.

Furthermore, 8 is the output of flip-flop 7 and 2
An exclusive OR circuit 9 outputs an exclusive OR with the frequency divider circuit 4, and a divide-by-2 circuit 9 divides the output of the exclusive OR circuit 8 by two and supplies it to an output terminal 10.

FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG. 1.

Input terminal 1 is supplied with a clock signal CK shown in the top row of FIG. This clock signal CK
is divided by 3 in the frequency divider circuit 3, and is supplied to the D input terminal of the flip-flop 7 as the 3-frequency divided clock signal ck shown in the second stage of FIG.
On the other hand, the frequency selection signal supplied to input terminal 2
SEL is supplied to the D input terminal of the flip-flop 5 and held therein in synchronization with the rising edge of the clock signal CK, producing an output a.

The output a of the flip-flop 5 is exclusive-ORed with the clock signal CK by an exclusive-OR circuit 6, and is supplied to the clock input terminal of the flip-flop 7 as an output b. In synchronization with the rise of this output b, the 3-frequency divided clock signal ck supplied to the D input terminal of the flip-flop 7 is held therein, and output c is generated. This output c
is the output d of the divide-by-2 circuit 4 by the exclusive OR circuit 8
The exclusive OR is performed on the resultant output e, which is supplied to the divide-by-2 circuit 9. The divide-by-2 circuit 9 divides the input e by two and supplies an output f to the output terminal 10 of this digital variable frequency circuit.

As shown on the left side of FIG. 2, while the frequency selection signal SEL applied to the input terminal 2 remains low, the output a of the flip-flop 5 is low, resulting in exclusive logic Output b from sum 6
has the same period and phase as the clock signal CK supplied to input terminal 1.

Therefore, the output c of the flip-flop 7 has a period three times that of the clock signal CK and
It rises and falls in synchronization with the rise of CK.
On the other hand, the output d of the frequency divider 4 is also a clock signal.
It rises at twice the period of CK and in synchronization with the rising edge of CK. As a result, 2 to the exclusive OR circuit 8
The rising and falling of the inputs c and d occur simultaneously, and the output e of the exclusive OR circuit 8 has a regular waveform as shown on the left side of FIG.

On the other hand, as shown on the right side of FIG. 2, when the frequency selection signal SEL supplied to the input terminal 2 rises to high level, the output of the flip-flop 5 synchronizes with the rise of the clock signal CK immediately thereafter. a goes high, and the output b from the exclusive OR 6 has the same period and opposite phase as the clock signal CK supplied to the input terminal 1.

Therefore, the output c of the flip-flop 7 has a period three times that of the clock signal CK and
It rises and falls with a time lag of half a cycle from the rising point of CK. On the other hand, the frequency divider circuit 4
Even after the rise of the frequency selection signal SEL, the output d continues to rise at twice the period of the clock signal CK and in synchronization with the rise of the clock signal CK. As a result, a time difference of half a period of the clock signal CK occurs between the rising and falling points of the two inputs c and d to the exclusive OR circuit 8, and an extra pulse due to this time difference is transmitted to the exclusive OR circuit 8. inserted into output e.

The divide-by-2 circuit 9 divides the output e of the exclusive OR circuit 8 into which an extra pulse is inserted as the frequency selection signal SEL changes, thereby doubling the frequency as the frequency selection signal SEL changes. The output f having a frequency of is outputted to the output terminal 10.

In this way, as the frequency selection signal SEL changes, the frequency of the signal f output from the output terminal 10 changes over a wide range of octaves.

In place of the above-mentioned 3 frequency divider circuit 3, generally N(3
or larger integer) frequency divider circuit can be used.

Effects of the Invention As explained in detail above, the digital variable frequency circuit of the present invention has a simple configuration including three frequency divider circuits, two flip-flops each, and an exclusive OR circuit, so that it can perform octave frequency circuits. The effect is that the digital frequency can be varied over a wide range.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a digital variable frequency circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the circuit shown in FIG. 1...Input terminal for clock signal CK, 2...Input terminal for frequency selection signal SEL, 3...3 frequency divider circuit, 4,9...2 frequency divider circuit, 5,7...flip-flop, 6, 8...Exclusive OR circuit, 1
0...Output terminal.

Claims (1)

[Claims for Utility Model Registration] An N frequency divider circuit that frequency divides a clock signal by N (N is an integer of 3 or more); a 2 frequency divider circuit that divides the frequency of the clock signal by 2; and a frequency selection signal that divides the frequency of the clock signal. a first flip-flop that holds the first flip-flop in synchronization with the clock signal; a first exclusive OR circuit that outputs an exclusive OR of the output of the first flip-flop and the clock signal; and the N-divider. a second flip-flop that holds the output of the circuit in synchronization with the output of the first exclusive OR circuit;
The present invention is characterized by comprising a second exclusive OR circuit that outputs an exclusive OR with the frequency divider circuit, and a divide-by-2 circuit that divides the output of the second exclusive OR circuit by two. Digital variable frequency circuit.