JPS61245648A - Injection synchronous type pulse generating circuit - Google Patents

Abstract

PURPOSE:To produce a group of pulses which are synchronous with phase of the frame of a transmission line by resetting a dividing circuit for each frame by the frame pulse extracted from the transmission line. CONSTITUTION:The output clock frequency of a clock source 1 is set previously at an integer multiple of the clock output 5. A dividing circuit 2 has an asynchronous resetting function divides the clocks supplied from the source 1 and resets these clocks forcibly for each frame by the frame pulse 3 to make synchronous with phase between the output 5 and the pulse 3. The circuit 2 is formed by cascading the desired number of 2-dividing circuits or n-dividing circuits to obtain a dividing ratio production of the desired output 5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an injection-locked communication system that is characterized in that it easily generates a group of pulses that are phase-synchronized with frame pulses extracted from a transmission path in a synchronous communication system. This invention relates to a pulse generation circuit.

[Conventional technology]

Conventionally, this type of synchronous pulse generation circuit inputs a frame pulse extracted from a received transmission signal and a clock pulse sent from the transmitting side, and outputs a signal obtained by dividing the clock pulse using a phase-locked loop (PLL) or Delayed phase-locked loop 1) Phase synchronization with frame pulses was achieved using a PLL circuit.

Pulse generation circuits using such PLLs are excellent in terms of versatility and stability, but when used in systems with loose jitter standards, for example, when precise stability is not required for the clock transmitted from the line termination device to the terminal. However, the drawbacks are that it is complicated and requires a large number of parts, the synchronization pull-in time is long, and the circuit adjustment requires a considerable number of man-hours.

[Purpose of the invention]

An object of the present invention is to provide an injection-locked pulse generation circuit that can easily form a pulse signal phase-synchronized with a frame pulse extracted from a transmission line without using PI and L, and that has a small number of components. .

[Structure of the invention]

According to the present invention, a clock source and a frequency divider circuit having an asynchronous reset function and dividing the clock frequency are provided, and the frequency divider circuit is reset for each frame by a frame pulse extracted from a transmission path. , an injection-locked pulse generation circuit is obtained which is characterized in that it generates a group of pulses that are phase synchronized with the frame of the transmission line.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, clock source (O20) 1 is clock output 5
This is an oscillator that generates a clock with sufficient precision to meet the standards required by the industry. The output frequency of this clock source is set in advance to be a multiple of the output βi.

The frequency divider circuit ([IV) 2 has an asynchronous reset function, and can divide the clock from the clock source 5 and forcibly reset it for each frame using the frame pulse (FP) 3 that arrives periodically. The clock output 5 is phase-synchronized with the frame pulse 3.

Such a frequency divider circuit 2 is made by cascading as many frequency divider circuits as shown in FIG. 2a or 2b as necessary to obtain a frequency division ratio for generating the desired clock output 5. .

FIG. 2a is a frequency divider circuit with a frequency division ratio of 2 and has a D flip-flop circuit 8, which supplies the frame pulse 3 to the reset (6) input and the clock 4 to the clock input (CK).

Figure 2b shows a frequency divider circuit with a frequency division ratio n, including a synchronous counter 9 with an asynchronous reset function and a synchronous load function, and a carry generation circuit (CAR) 10 that outputs 0 only when the output of this counter is n -1. , and includes a D flip-flop 11 that delays the carry output 12 of , and by one clock.

The operation when the frequency dividing circuit 2 used in FIG. 1 is composed of one stage of the n frequency dividing circuit shown in FIG. 2b will be explained with reference to the timing chart shown in FIG. 3.

The synchronous counter 9 shown in FIG. 2b has a frame pulse 3
If there is no input, the clock input 4 shown in Fig. 3(a)
, and repeats the counting of 0, 1, . d)
When the frame pulse 3 is input, the synchronous counter 9 and the D flip-flop 11 are reset.

Now, when the time one frame after the arrival of the immediately preceding frame pulse is φ, the next frame pulse will be the third frame pulse.
If φ and φ also arrive a little earlier as shown in FIG. The waveforms of clock output 5 are shown in Fig. 3 (f), (g), and (
h). Conversely, the frame pulse is shown in Figure 3 (
When φ also arrives a little later as in i), the waveforms of the count value, carry, and clock output are as shown in Figure 3 (rb),
As shown in (c) and (d), they are not affected by the frame pulse 3. Therefore, when the n frequency divider circuit shown in Fig. 3 (a) is placed at the first stage of the frequency divider circuit, the maximum clock 4 (Fig. 3 (a)
)) causes a counting error of one clock and accompanying jitter.

=5- Next, if the frequency divider circuit used in the 11th!1 consists of the frequency divider circuits shown in Figure 2b connected in cascade, the operation of the frequency divider circuits in stages other than the first stage is shown in Figure 4. This will be explained with reference to the timing chart shown below.

The operation when frame pulse 3 is not input is exactly the same as the first stage (first stage), with clock manual power of 4 and count value Q.
, carry 12. The waveform of clock output 5 is shown in Figure 4(a).
, tb), (C), (d). In this case, the clock input 4 is the clock output of the frequency dividing circuit at the previous stage. Now, when frame pulse 3 arrives earlier than φ as shown in FIG. 4(e), synchronous counters 9 and D
Flip-flop 11 is immediately reset and the count value Q
, carry 12. Clock output 5 is shown in Figure 4 (g) and (h).
, the phase is advanced as in (1).

Furthermore, when this frame pulse is generated, the phase of the clock input supplied from the previous stage follows the frame pulse as shown in Figure 4(f), so no counting error occurs, and the phase of the clock output simply changes. It only deviates by following the frame pulse. Conversely, the frame pulse is shown in Figure 4 (j).
If it arrives a little earlier than φ, as in the case, the count value Q
, carry 12. The waveforms of the clock output 5 are as shown in FIGS. 4(b), (e), and td), and are not affected by the frame pulse.

Therefore, by vertically connecting the circuits shown in Figures 2a and 2b, it is possible to obtain a clock output with any division ratio that is phase-synchronized and follows the frame pulse, and the amount of jitter is determined by the jitter of the input frame pulse. The value is approximately equal to the amount plus at most one clock of the clock supplied from the clock source.

The frame pulse width needs to be at least wide enough for the output Q of the D flip-flop to complete the transition from O to 1.

〔Effect of the invention〕

As explained above, the present invention uses several frequency divider circuits or n frequency divider circuits that are connected in cascade to generate pulses 8 + 1 + 2, which are phase-synchronized with the frame pulse extracted from the transmission line, without using a PLL. Since the number of parts can be reduced, the synchronization pull-in time can be shortened, and the number of adjustment man-hours can be saved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2a,
Figure 2b is a circuit diagram of the frequency divider circuit used in Figure 1, and Figures 3(a), -, (1) show the circuit elements in Figure 2b used in the first stage of the frequency divider circuit used in Figure 1. Timing diagrams showing operations at certain times, FIG. 4(a), -. U) is a timing diagram showing the operation when the circuit element of FIG. 2b is located at a position other than the first stage of the frequency dividing circuit used in FIG. 1. 1... Clock source, 2... Frequency divider circuit,
3...Frame pulse, 4...Clock, 5...Clock output, 6...D flip-flop, 9...Synchronous counter , 10
...Carry generation circuit, 11...D flip-flop, 12...Carry. Hehehehehehehe 5 g -33g g bS5 'S Kokomi Q ``g mo S et al ≦゛9S Procedural amendment (method) % formula % 1, Indication of case 1982 Patent Application No. 2620
No. 45 No. 2, Title of the invention: Injection-locked pulse generation circuit 3, Relationship to the amended case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation (Contact address: NEC Corporation) (Company Patent Department) 5. "Brief explanation of drawings" column 6 of the specification to be amended Contents of the amendment (1) Specification, page 8, line 4: "Figure 3 (a), -. i) is” is corrected to “Figure 3 is”. (2) Same, page 8, lines 6 to 7, “Figure 4 (a)
. ~, (j) is corrected to ``Jftr Figure 4''.

Claims (1)

[Claims] It has a clock source and a frequency divider circuit that has an asynchronous reset function and divides the frequency of the clock, and by resetting the frequency divider circuit for each frame using a frame pulse extracted from the transmission line, the frame and phase of the transmission line can be adjusted. An injection-locked pulse generation circuit characterized by generating a group of synchronized pulses.