JPS62295517A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To increase the phase shift quantity with comparatively simple constitution by inserting a phase shift circuit between a frequency divider and a phase comparator in a PLL type synchronizing oscillator where an output of a voltage controlled oscillator (VCO) is fed back to the phase comparator via the frequency divider. CONSTITUTION:Since the phase circuit 4 is connected to the output side of a frequency divider 2, the frequency applied to the circuit 4 is subject to 1/N division by the frequency divider 2, the phase shift is N times with respect to a slow signal whose period is N time. That is, in using a CR phase shift circuit 4 whose phase shift ratio is 10% the same as a conventional circuit, the period is 10% to the period being a mltile of N and the phase shift is N times the conventional device natrually. In selecting the frequency division of the frequency dividers 21, 22 as 1/n, 1/m, and in comparison with the frequency division ratio N of the frequency divider 2, the N is selected as nxm=N (e.g., 20X50=1000, then n=20 and the phase shift is 20 times of the conventional device). In this case, a frquency division ratio not extremely large is used, then the oepration stablity is much improved.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In a phase-locked loop type synchronous oscillation circuit, the output pulse waveform is not transferred on the output side of the voltage controlled oscillator, and the frequency divider and phase This is a synchronous oscillation circuit in which a phase shift circuit is inserted between the comparator and a large phase shift amount.

[Industrial Application Field] The present invention relates to a phase-locked loop (hereinafter referred to as P
This invention relates to a circuit that can obtain a large amount of phase shift in a synchronous oscillation circuit (abbreviated as LL) type.

When it is desired to obtain a pulse train with a large phase shift amount using a PLL type synchronous oscillation circuit, a phase shift circuit using a CR is not sufficient, so a circuit that can obtain a large phase shift has been desired.

[Prior Art] When obtaining a clock pulse train synchronized with a horizontal synchronizing signal used in a plasma display device, it is necessary to accurately align the pulse rise time of the signal used in the plasma display device and the rise time of the clock pulse train. There is. That is, by matching the pulse repetition frequencies and eliminating the phase difference, a phase shift circuit was added to the rear stage of the PLL type synchronous oscillation circuit as the pulse generation circuit, as shown in FIG. In FIG. 4, a pulse train repetition frequency IMIIz of approximately 1/+000, 1kllz, is input to the input terminal 6 as a reference signal. The phase comparator circuit 2 compares the phases of the reference signal and the output of the frequency divider 2, and outputs a signal with a magnitude corresponding to the phase difference between the two as a direct current via a low-pass filter built in the phase comparator 1. Only signals close to 2 are applied to the voltage controlled oscillator 3VCO. When it is applied, it is fed back and applied in a direction that reduces the phase difference. The voltage controlled oscillator 3 oscillates a sine wave of a predetermined frequency, and the phase is shifted to the phase shift circuit 4 . At that time, waveform shaping is performed using a limiter or the like to obtain a pulse waveform. Further, a part of the output of the voltage controlled oscillator 3 is applied to the 1/N frequency divider 2, for example, 1/N.
The frequency is divided by /1000. The output of the frequency divider 2 is phase-compared with the input reference signal in the phase comparator l as described above.

Here, the output pulse train of the voltage controlled oscillator 3 is phase shifted in the phase shift circuit 4. This circuit is constructed by cascading operational amplifiers 41, 43 and phase shifter 42. The phase-shifted output is taken out from terminal 5 as a pulse train.

[Problems to be Solved by the Invention] The circuit operation of the CR phase shifter as shown in FIG. 4 has the disadvantage that a large phase shifter cannot be obtained. That is, as shown in the waveform diagram shown in FIG. 5, the pulse waveform at the input terminal of the operational amplifier 41 becomes to(1)! before the next pulse falls. seconds)
Assuming that, the waveform (2) based on the time constant of CR is limited at a predetermined threshold level vth by the operational amplifier 43 to obtain a pulse waveform (2). At this time, the especially thick line portion of the waveform (2) is based on the charging/discharging operation of CR, and is a curve related to the time constant of CR. The curve cannot have a waveform with an extremely small slope due to the limiter level vth and the repetition period. Therefore, the delay amount td of the pulse waveform is t.

This is about 10% (100 ns) of the current time. Therefore t.

When delaying to a large value over the entire circuit, it was necessary to connect at least 10 stages of phase shift circuits 4 in cascade.

Such circuits have become expensive and impractical.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous oscillation circuit which can improve the above-mentioned drawbacks and can increase the amount of phase shift with a relatively simple configuration.

[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. In FIG. 1, 1 is a phase comparator, 2 is a frequency divider, 3 is a voltage controlled oscillator (VCO), 5 is a pulse train output terminal, and 6 is a reference signal input terminal. In a PLL type synchronous oscillator in which the output of the VCO 3 is fed back to the phase comparator 1 via the frequency divider 2, the present invention has a phase shift circuit 4 inserted between the frequency divider 2 and the phase comparator 1. Features.

[Function] In FIG. 1, the phase shift circuit 4 is connected to the output side of the frequency divider 2, so the frequency applied to the phase shift circuit 4 is 1/N by the frequency divider 2, and the repetition period is For a signal that is N times slower, a phase shift value that is N times larger can be obtained. That is, if a CR phase shift circuit 4 with a phase shift ratio of 10%, which is the same as the conventional one, is used, the value will be 10% of the period N times, and the amount of phase shift will naturally be N times the value of the conventional one.

In Fig. 2 showing the operating waveforms of Fig. 1, ■ is the frequency divider 2.
, and ■ indicates the output signal of the phase shift circuit 4. ■-1
is the initial output pulse train of VCO3, ■-2 is the phase shift circuit 4
3 shows the output pulse train of VCO 3 after operation.

Since t,'=N-t, td'=N-td, and it can be seen that td' becomes a value N times larger.

[Embodiment FIG. 3 is a diagram showing the configuration of an embodiment of the present invention. In Fig. 3, 21 and 22 are both frequency dividers, and the frequency division ratio is l/n, 1
/m is shown. Frequency division ratio N of frequency divider 2 in Fig. 1
compared to nxm-N (e.g. 20 x 50 =
1000). In FIG. 3, the same reference numerals as in FIG. 1 indicate similar parts. In FIG. 3, since it is n-20, a phase shift amount 20 times larger than that of the conventional case can be obtained. In this case, compared to FIG. 1, the frequency division ratio does not have to be extremely large, so the operational stability is improved.

[Effects of the Invention] In this manner, according to the present invention, a synchronous oscillation circuit with a large amount of phase shift can be obtained with a simple configuration that only requires changing the connection of the frequency dividing circuit.

[Brief explanation of the drawing]

Figure 1 shows the principle configuration of the present invention. Figure 2 is the operating waveform diagram of Figure 1. Figure 3 shows the configuration of an embodiment of the invention. Figure 4 shows the configuration of a conventional synchronous oscillation circuit. The figure shown in FIG. 5 is an operation waveform diagram of FIG. 4. ■ - Phase comparator 2 - Frequency divider 3 - Voltage controlled oscillator 4 - Phase shift circuit 5 - Output terminal Patent applicant Fujitsu Limited Agent Patent attorney Eisuke Suzuki Phase comparator circuit Voltage controlled oscillator Figure 1

Claims (1)

[Claims] A phase comparator (1) to which a reference signal is input, a voltage controlled oscillator (3) to which its output is applied, and a voltage controlled oscillator (
3) A frequency divider (
2), which receives the output of the voltage controlled oscillator (3) from the output terminal (5) via the phase shifting circuit (4), wherein the phase shifting circuit (4) is connected to the voltage controlled oscillator It is removed from the output terminal (5) side of the oscillator (3) and the frequency divider (2) and phase comparator (
1) A synchronous oscillation circuit characterized by being inserted between.