JPH0552110B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a video digitizing device that digitizes analog video signals for arbitrary screen conversion.

(Prior art and its problems) Figure 5 is a block diagram of a conventional video digitizing device that digitizes an analog video signal such as a computer video signal for displaying stock price information sent from a securities company. 1 is A/
2 is a D converter; 2 is a video memory that stores digitized video signals; 3 is a sync signal separation circuit that extracts horizontal and vertical sync signals from the input video signal and separates and reproduces them; 5 is a sync signal separation circuit This is a phase comparison circuit that compares the phase of the horizontal synchronizing signal separated and outputted by the frequency divider 8 with the phase of the output from the frequency divider 8. This phase comparator circuit 5 has a sixth
As shown in Figure a, it is composed of a phase comparator 12 and a charge pump 13. This phase comparator 12
As shown in the timing chart in Figure 6b, the system detects the rising edge of the input signal when it changes from low to high level, compares the phase and frequency, and if the input signal is ahead of the input signal, the input signal is A positive pulse P ₁ is output during the time from the rise of the input to the rise of the input, and conversely, if the input is ahead of the input, a negative pulse P ₂ is output during the time from the rise of the input to the rise of the input.
output, and outputs a phase comparison signal that is high impedance at other times. Phase comparator 1
The output signal No. 2 is input to a charge pump 13 having a characteristic that the output voltage changes depending on the degree of phase advance, as shown in FIG. 6c. Returning to FIG. 5, 6 is an LPF for making the output voltage from the phase comparison circuit 5 the control voltage of the next voltage controlled oscillator 7;
7 is a voltage controlled oscillator that outputs a multiplied sample clock controlled by its control voltage; 8
is a frequency divider that divides the frequency of the sample clock by the multiplication factor, and the above-mentioned 5 to 8 constitute the PLL circuit 4, which synchronizes with the input horizontal synchronization signal and whose repetition frequency is multiplied. occurs. That is, by feeding back the output obtained by dividing the currently output sample clock by a factor of 1 by the frequency divider 8 to the phase comparator circuit 5, the phase difference with the horizontal synchronizing signal separated and reproduced from the input video signal is calculated. The sample clock is always synchronized with the input synchronization signal. The output voltage corresponding to the phase difference detected by the phase comparison circuit 5 is output as a control voltage by the LPF 6,
The voltage controlled oscillator 7 generates a sample clock with a repetition frequency that is synchronized with the horizontal synchronization signal and multiplied.
By outputting from the PLL circuit 4 and feeding it to the A/D converter 1, the input video signal is A/D converted at a timing synchronized with the sample clock. minutes are stored in the video memory 2.

As mentioned above, in the conventional device that A/D converts and digitizes the input video signal using a sample clock of a multiplied frequency that is synchronized with the horizontal synchronization signal that is separated and reproduced from the input video signal, the result of the vertical synchronization signal is If the input video signal is such that a cut pulse (SP) with the same period as the horizontal synchronization signal is inserted during the line period, and a stable horizontal synchronization signal can be obtained on the receiving side, the sample clock is also stable and stable digitization is possible. There is no problem as this is done.

However, in private video signal transmission using computers other than public broadcasting, there are some differences in the synchronization signals depending on the production period of the equipment and the mix of manufacturers, and a cutting pulse is inserted in the retrace period of the vertical synchronization signal. Other methods are also used. Video digitization equipment is used in scanning line conversion equipment, etc. that digitizes various video input signals transmitted from multiple computer stations and changes the screen size, etc. Highly accurate digitization is also required.

FIG. 7 is a time chart of the composite synchronization signal included in the input video signal, and the horizontal and vertical synchronization signals that are separated and reproduced.

FIG. 7a is a time chart when a cut pulse (SP) is inserted in the retrace period _Tv of the vertical synchronization signal of the composite synchronization signal, and FIG. 7B is a time chart when there is no cut pulse. In case a, horizontal synchronizing pulses are continuously regenerated by cutting pulses in the separated and regenerated horizontal synchronizing signal, but in case b, horizontal synchronizing pulses are continuously regenerated during the retrace period.
There is no horizontal synchronization pulse in _Tv , and during this period, conventional equipment had problems with sample lock synchronization and multiplication frequency for digitization becoming unstable.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems and to provide a signal processing system for input video signals in which a cut pulse for stabilizing the horizontal synchronization signal is not inserted in the retrace period of the vertical synchronization signal. An object of the present invention is to provide a video digitizing device that generates a stable sample clock and performs digital conversion.

(Structure and Operation of the Invention) The video digitizing device of the present invention is provided with a circuit that generates an inhibit pulse calculated from a vertical synchronization signal separated and reproduced from a composite synchronization signal of an input video signal without a cut pulse, and The present invention is characterized in that it is configured to eliminate unstable elements in the retrace period and to generate a stable sample clock that is frequency-multiplied in synchronization with the separated and reproduced horizontal synchronizing signal.

The details of the present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram of the main parts of a video digitizing apparatus equipped with an inhibit pulse generating circuit 11 showing one embodiment of the present invention. In the figure, 1 is A/
D converter, 2 is a video memory, 3 is a synchronizing signal separation circuit, 10 is a phase comparison circuit that does not perform a comparison operation while the inhibit pulse is applied, 6 is a low pass filter (LPF), 7 is a voltage controlled oscillator, 8 is a frequency divider,
Reference numeral 11 denotes an inhibit pulse generation circuit that inputs a vertical synchronizing signal and outputs an inhibit pulse, and circuits 6 to 8, 10, and 11 constitute the main part of the present invention.
This is a PLL circuit 9.

In FIG. 1, a phase comparison circuit 10 detects the phase difference between the horizontal synchronization signal separated and reproduced from the input video signal by the synchronization signal separation circuit 3 and the output obtained by dividing the frequency of the current sample 9. By applying this as a control voltage to the voltage controlled oscillator 7, a sample clock whose repetition frequency is multiplied in synchronization with the input horizontal synchronizing signal is generated. The inhibit pulse is output by inputting a vertical synchronizing signal to the inhibit pulse generating circuit 11 and setting an arbitrary inhibit pulse width. This inhibit pulse is applied to the phase comparator circuit 10 to stop the output of the phase comparator circuit 10 during a time that sufficiently includes the retrace period of the vertical synchronization signal. Therefore, since the control voltage input to the voltage controlled oscillator 7 does not vary during that time, the sample clock is output in synchronization with the horizontal synchronizing signal. This sample clock is A/
The signal is input to the D conversion circuit 1, A/D converted at a timing synchronized with the input video signal sample clock, and stored in the image memory 2.

FIG. 2a is a block diagram showing a detailed configuration example of the phase comparator circuit 10, which is composed of a phase comparator 14 and a charge pump 13. b is a timing chart for explaining the circuit operation of a, and c is a characteristic diagram of the charge pump 13. In the figure,
The horizontal synchronization signal and the output from the frequency divider 8 are phase-compared by the phase comparator 14, but during the pulse width T _s of the inhibit pulse, no phase comparison operation is performed, the output terminal becomes high impedance, and the phase comparator 14 no output appears.

FIG. 3 is a block diagram and a time chart showing a detailed embodiment of the inhibit pulse generating circuit 11 which constitutes the main part of the present invention. In the figure, 15 is an inverter that inverts the input vertical synchronization signal, 16, 17
is a programmable tile counter.
This programmable timer counter 16,1
7 is a circuit that outputs a low level at the rising edge of the input signal pulse, and outputs a high level after counting an arbitrarily set number of times by inputting a timer clock.

The pulse width T _s of the inhibit pulse is set so as to have a margin before and after the retrace period T _v of the vertical synchronization signal. In reality, the margin times T _e and T _d before and after this are set to about several to 20 horizontal synchronizing pulses. Referring to the time chart in FIG. 3b, the vertical synchronizing signal input to the inhibit pulse generating circuit 11 has a waveform inverted by the inverter 15 and is input to the programmable timer counter 16. Here, a prohibition end pulse with a pulse width T _d set so that the trailing edge of the prohibition pulse is t ₄ delayed by the margin time T _d from the trailing edge t ₃ of the retrace period T _v is generated and output. The programmable timer counter 17 inputs this prohibition end pulse, sets the time T _n from the trailing edge t ₄ to the rising edge t ₁ of the prohibition pulse, and outputs the prohibition pulse. In other words, this set time T _n is a time point t ₁ earlier by the margin time T _e than the start time t ₂ of the retrace period T _v
Set the inhibit pulse to rise with . As described above, the programmable timer counter 16,
17 allows setting the pulse width T _s of the inhibit pulse. In this way, the pulse width T _s of the inhibition pulse corresponding to input video signals with different synchronization signals can be arbitrarily set.

FIG. 4 is a timing chart of the output voltages of the synchronizing signals, inhibit pulses, and phase comparator circuit 10.

As shown in the figure, the retrace period of the vertical synchronization signal T _v
An inhibit pulse is generated based on a vertical synchronizing signal separated and reproduced from a composite synchronizing signal without a cutting pulse, and the output of the control voltage of the phase comparator circuit 10 can be inhibited as shown below.

(Effects of the Invention) As explained in detail above, according to the present invention,
A sample clock synchronized with the composite synchronization signal can be generated, and a stable sample clock can be supplied even for input video signals that do not have cutting pulses for horizontal synchronization stabilization during the retrace period of the vertical synchronization signal. I can do it. Further, by arbitrarily changing the pulse width of the inhibit pulse, it is possible to easily deal with various different composite synchronization input video signals.

Therefore, in a video digitizing device, it is particularly effective when performing stable digital conversion of an input video signal regardless of the presence or absence of a cutting pulse.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram, time chart, and characteristic diagram of the phase comparator circuit of the present invention. FIG. 3 is a block diagram and time chart showing a part of the circuit of the present invention in detail. FIG. 4 shows the operation of the present invention. Figure 5 is a block diagram of a conventional circuit; Figure 6 is a block diagram, time chart and characteristic diagram of a conventional phase comparison circuit; Figure 7 is a time chart explaining the operation of the conventional circuit. . 1...A/D converter, 2...image memory, 3...
...Synchronization signal separation circuit, 4, 9...PLL circuit, 5,
10... Phase comparison circuit, 6... LPF, 7... Voltage controlled oscillator, 8... Frequency divider, 11... Inhibition pulse generation circuit, 12, 14... Phase comparator, 13...
...Charge pump, 15...Inverter, 16, 17
...Programmable timer/counter.

Claims (1)

[Scope of Claims] 1. The analog input is synchronized with a horizontal synchronization signal separated and reproduced from a composite synchronization signal included in an analog input video signal, and the sample clock has a repetition frequency that is multiplied by the pulse repetition frequency of the horizontal synchronization signal. A video digitizing device that samples a video signal and converts it into a digital signal, comprising: a synchronization signal separation circuit that separates and reproduces a horizontal synchronization signal and a vertical synchronization signal from the analog input video signal and outputs the separated signals; a phase comparator circuit that takes the input as an input and compares the phase with the other input; a voltage controlled oscillator that inputs the output of the phase comparator circuit as a control voltage via a loop filter and outputs the sample clock; and an output frequency of the voltage controlled oscillator. a frequency divider that divides the frequency by the multiplied value and inputs the frequency to the other input of the phase comparator circuit; an inhibit pulse generation circuit that generates an inhibit pulse with a pulse width that ends later than the end of the retrace period and inputs the inhibit pulse to the phase comparator circuit in order to stop the output of the phase comparator circuit for a time of the pulse width; A video digitizing device comprising: