JPH0318182A - Video digitizer - Google Patents

Abstract

PURPOSE:To attain stable digital conversion of an input video signal by giving an inhibit pulse generated through the input of a vertical synchronizing signal to a phase comparator circuit and stopping a phase comparator output at a time including sufficiently a blanking period of the vertical synchronizing signal. CONSTITUTION:A horizontal synchronizing signal separated and reproduced by a synchronizing separator circuit 3 from an input video signal and an output and its phase difference obtained from a present sample clock through frequency-division by a frequency divider 8 are detected by a phase comparator circuit 10 and the detected output is given to a voltage controlled oscillator 7 by an LPF 6 as a control voltage to generate a sample clock synchronously with a horizontal synchronizing signal and whose frequency is multiplied. An inhibit pulse is outputted from an inhibit pulse generating circuit 11 set with an optional inhibit pulse width through the input of a vertical synchronizing signal. The inhibit pulse is given to the phase comparator circuit 10 to stop the output of the phase comparator circuit 10 at a time including the blanking period of the vertical synchronizing signal sufficiently.

Description

TECHNICAL FIELD The present invention relates to a video digitizing device that digitizes analog video signals for arbitrary screen conversion.

(Prior art and its problems) Fig. 5 is a block diagram of a conventional video digitizing device that digitizes an analog video signal such as a computer video signal for displaying stock price information sent from a securities company. 1 is an A/D converter, 2 is a video memory that stores the digitized video signal, and 3 is a synchronization signal separation circuit that extracts the horizontal synchronization signal ■ and vertical synchronization signal ■ from the input video signal and separately reproduces them. , 5 is a phase comparator circuit that compares the phase of the horizontal synchronizing signal (2) separated and outputted by the synchronizing signal separation circuit 3 with the phase of the output (2) from the frequency divider 8. As shown in FIG. 6(a), this phase comparator circuit 5 includes a phase comparator l2 and a charge pump l3. As shown in the timing chart of FIG. 6(b), this phase comparator 12 receives input signals
The rising edge that changes from OW to Illight level is detected and the phase and frequency are compared. If the input ■ is ahead of the input ■, a positive pulse P, On the other hand, if the input ■ is ahead of the input ■, the input ■ is output from the rising edge of the input ■.
A negative pulse P2 is output during the time until the rise of , and a phase comparison signal (2) which is high impedance is output at other times. The output signal ■ of the phase comparator 12 is shown in FIG. 6(C).
As shown in FIG. 2, the output voltage is input to a charge pump 13 which has a characteristic that the output voltage changes depending on the degree of phase advance. Fifth
Returning to the figure, 6 is an LPF for making the output voltage from the phase comparator circuit 5 the control voltage for the next voltage controlled oscillator 7, and 7 is a voltage controller that outputs a multiplied sample clock controlled by the control voltage. The oscillator 8 is a frequency divider that divides the sample clock into a multiplication factor, and
-8 constitute a PLL circuit 4, which generates a sample clock whose repetition frequency is multiplied in synchronization with the input horizontal synchronizing signal (2). That is, by feeding back the output (2) obtained by dividing the currently output sample clock to 1 by the frequency divider 8 to the phase comparator circuit 5, the output (2) can be compared with the horizontal synchronization signal (3) separated and reproduced from the input video signal. The phase difference is detected and the sample clock is always synchronized with the input synchronization signal. The output voltage corresponding to the phase difference detected by the phase comparator circuit 5 is output as a control voltage by the LPF 6, and the voltage controlled oscillator 7 generates a sample clock with a multiplied repetition frequency in synchronization with the horizontal synchronization signal ■.
By outputting it from the LL circuit 4 and feeding it to the A/D converter 1, the input video signal (2) is A/D converted at a timing synchronized with the sample clock, and the input video signal is converted into an A/D signal for one screen per scan, that is, the input scanning line. Several minutes are stored in the video memory 2.

As mentioned above, in the conventional device that A/D converts and digitizes the input video signal using a sample clock of a multiplied frequency synchronized with the horizontal synchronization signal (■) that is separated and reproduced from the input video signal (2), the output of the vertical synchronization signal is If the input video signal is such that a cut pulse (SP) with the same period as the horizontal synchronization signal is inserted into the line period and a stable horizontal synchronization signal can be extracted on the receiving side, the sample clock is also stable and stable digitization is possible. There is no problem because it is done. However, in private video signal transmission by computers other than public broadcasting, there are some differences in the same W1 signal depending on the production period of the equipment and the mix of manufacturers, and a cutting pulse is inserted in the retrace period of the vertical synchronization signal. Other methods are also used. Video digitization equipment is used in scanning line conversion equipment that digitizes various video input signals transmitted from multiple computer stations and changes the screen size, etc. Highly accurate digitization is also required.

FIG. 7 is a time chart of the horizontal synchronization signal (2) and the vertical synchronization signal (2) which are separately reproduced from the composite synchronization signal contained in the input video signal.

FIG. 7(a) shows the case where a cutting pulse (SP) is inserted in the retrace period TV of the vertical synchronization signal of the recovered good friend signal ■.
(b) is a time chart when there is no cutting pulse. In case (a), horizontal synchronization pulses are continuously reproduced in the separated and reproduced horizontal synchronization signal ■ by the cutting pulse, but in case (b), there is no horizontal synchronization pulse in the blanking period TV, and during this period Conventional devices have the problem that sample lock synchronization and multiplication frequency for digitization become unstable.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems and to provide a signal processing system for input video signals in which a cut pulse for stabilizing the horizontal synchronization signal is not inserted in the retrace period of the vertical synchronization signal. An object of the present invention is to provide a video digitizing device that generates a stable sample clock and performs digital conversion.

(Structure and operation of the invention) The video digitizing device of the present invention is provided with a circuit that generates an inhibit pulse calculated from a vertical synchronization signal separated and reproduced from a composite synchronization signal of an input video signal without a cut pulse, and generates a vertical synchronization signal. The present invention is characterized in that it is designed to eliminate unstable elements in the retrace period and to generate a stable sample clock that is frequency-multiplied and synchronized with the separated and reproduced horizontal synchronizing signal.

The details of the present invention will be explained below with reference to the drawings.

FIG. 1 shows an inhibition pulse generation circuit 1 showing an embodiment of the present invention.
1 is a block diagram of the main parts of a video digital quiz device equipped with 1. In the figure, 1 is an A/D converter, 2 is a video memory, 3 is a synchronization signal separation circuit, 10 is a phase comparison circuit that does not perform a comparison operation while an inhibit pulse is applied, and 6 is a low-pass filter (LPF). ), 7 is a voltage controlled oscillator, 8 is a frequency divider, and 11 is a vertical synchronization signal ■ to input an inhibit pulse ■
This is a prohibition pulse generation circuit that outputs 6 to 8 and 10.
．． A circuit 11 is a PLL circuit 9 that constitutes the main part of the present invention.

In Fig. 1, a phase comparison circuit l calculates the phase difference between the horizontal synchronization signal (■) separated and reproduced from the input video signal by the synchronization signal separation circuit (3) and the output (■) obtained by dividing the current sample clock.
By supplying the detection output (2) to the voltage controlled oscillator 7 as a control voltage by the LPF 6, a sample clock whose repetition frequency is multiplied in synchronization with the input horizontal signal (2) is generated. The prohibition pulse ■ is output by inputting the vertical synchronizing signal ■ to the prohibition pulse generation circuit l1 and setting an arbitrary prohibition pulse width. This inhibition pulse (2) is applied to the phase comparator circuit 10 to stop the output of the phase comparator circuit 10 during a time that sufficiently includes the retrace period of the vertical synchronization signal (2). Therefore, since the control voltage input to the voltage controlled oscillator 7 does not change during that time, the sample clock is output in synchronization with the horizontal synchronizing signal (2). This sample clock is input to an A/D conversion circuit 1, and the input video signal is A/D converted at a timing synchronized with the sample clock and stored in an image memory 2.

FIG. 2(a) is a block diagram showing a detailed configuration example of the phase comparator circuit 10, in which the phase comparator 14 and charge bomb 1
Constructed by 3. (b) is a timing chart for explaining the circuit operation of (a), and (C) is a characteristic diagram of the charge pump 13. In the figure, the horizontal synchronizing signal and the output (2) from the frequency divider 8 are compared in phase by a phase comparator l4, but the pulse width of the inhibition pulse (2) is T. During this period, the phase comparison operation is not performed, the output terminal becomes high impedance, and the output (2) of the phase comparator 14 does not appear.

FIG. 3 shows an inhibition pulse generation circuit 1 which constitutes the main part of the present invention.
1 is a block diagram and a time chart showing a detailed embodiment of the invention. In the figure, 15 is an inverter that inverts the input vertical synchronizing signal 1, 16. 17 is a programmable tile counter. The programmable timer counters 16 and 17 go low at the rising edge of the input signal pulse.
This circuit outputs the o-level, inputs a timer clock, counts an arbitrarily set number of times, and then outputs the 11ight level.

The pulse width T of the inhibition pulse (2) is set to a width that allows some margin before and after the retrace period TV of the vertical synchronizing signal (2). Actually, the margin time before and after that is T. and T are set to about several pulses to 20 horizontal synchronizing pulses.

To explain with the time chart of FIG.
The waveform (2) inverted by 5 is input to the reprogrammable timer counter 16. Here, a prohibition end pulse ■ having a pulse width T4 set so that the green after the prohibition pulse ■ becomes t4 delayed by a margin time T4 from the trailing edge L3 of the retrace period TV is generated and output. The programmable timer counter 17 inputs this prohibition end pulse ■ and calculates the time T from the trailing edge t4 to the rising edge 1+ of the prohibition pulse ■.
．． Set and output prohibition pulse ■. That is, this set time T. is set so that the prohibition pulse ■ rises at time 1, which is earlier than the start time t2 of the retrace period TV by a margin time T8. As described above, the programmable timer counter 16. Pulse width T of pulse ■ prohibited by IT,
can be set. In this way, it is possible to arbitrarily set the pulse intensity T of the inhibition pulse (2) corresponding to the input video signals of different synchronization signals.

FIG. 4 is a timing chart of each of the companion signals (■) to (■), the inhibition pulse (■), and the output voltage (■) of the phase comparator circuit 10. As shown in the figure, an inhibition pulse ■ is generated based on the vertical synchronization signal ■ separated and reproduced from a composite synchronization signal without a cutting pulse during the retrace period TV of the vertical synchronization signal, and the phase comparator circuit 1
The output of a control voltage of 0 can be prohibited as shown in (■).

(Effects of the Invention) As described above in detail, according to the present invention, a sample clock synchronized with a composite synchronization signal can be generated, and a cutting pulse for stabilizing horizontal synchronization can be generated during the retrace period of a vertical synchronization signal. It is possible to supply a stable sample clock even to input video signals that are not stable. Further, by arbitrarily changing the pulse width of the inhibit pulse, it is possible to easily deal with various different composite synchronization input video signals.

Therefore, in a video digitizing device, it is particularly effective when performing stable digital conversion of an input video signal regardless of the presence or absence of a cutting pulse.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram, time chart and characteristic diagram of the phase comparator circuit of the invention, and Fig. 3 shows a part of the circuit of the invention in detail. A block diagram and a time chart, FIG. 4 is a time chart explaining the operation of the present invention, FIG. 5 is a block diagram of a conventional circuit, FIG. 6 is a block diagram, time chart, and characteristic diagram of a conventional phase comparator circuit, FIG. 7 is a time chart explaining the operation of the conventional circuit. ! ...A/D converter, 2...image memory, 3.
...Synchronization signal separation circuit, 4.9...PLL circuit,
5, IO...phase comparison circuit, 6...LPF, 7.
...Voltage controlled oscillator, 8... Frequency divider, 11...
Inhibition pulse generation circuit, 12. 14... Phase comparator, l3... Charge pump, 15... Inverter,
16. 17...Programmable timer/counter.

Claims (1)

[Scope of Claims] The analog input video signal is synchronized with a horizontal synchronization signal separated and reproduced from a composite synchronization signal included in the analog input video signal, and is synchronized with a sample clock having a repetition frequency that is multiplied by the pulse repetition frequency of the horizontal synchronization signal. A video digitizing device that samples and converts a digital signal into a digital signal, comprising: a synchronization signal separation circuit that separates and reproduces a horizontal synchronization signal and a vertical synchronization signal from the analog input video signal and outputs the separated signals; a phase comparison circuit that compares the phase with the other input, a voltage controlled oscillator that inputs the output of the phase comparison circuit as a control voltage via a loop filter and outputs the sample clock, and multiplies the output frequency of the voltage controlled oscillator as described above. a frequency divider that divides the frequency by a factor of 1 and outputs the frequency as the other input of the phase comparator circuit; and an inhibit pulse generation circuit that generates an inhibit pulse with a pulse width that ends later than the end of the phase comparison circuit, and inputs the inhibit pulse to the phase comparison circuit in order to stop the output of the phase comparison circuit for a time of the pulse width. A video digitizing device characterized by: