JPH0322764A - Clamping circuit - Google Patents

Abstract

PURPOSE:To process a video signal which has a different synchronizing signal automatically by varying the reference position of the reference voltage of a clamp level detecting circuit, a reference value to be compared with a refer ence voltage, and a clamp pulse position supplied to an analog clamping circuit according to the decision result of the system of an input video signal. CONSTITUTION:A synchronism decision circuit 22 which decides which of systems of clamping operation using the value of a clamp level period inserted in the vertical blanking period of the video signal as a reference voltage and clamping operation which uses a pedestal level set in a horizontal synchronizing signal period as a reference voltage is inputted switches the clamp level refer ence value, clamp level reference position, and clamp pulse position. Then one clamping circuit 2 performs the DC regeneration of an input video signal having a different synchronizing signal. Consequently, even video signals having differ ent synchronizing signals can be clamped automatically and correspondingly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a clamp circuit for television signals. Conventional technology Figure 6 (a) is an example of the waveform of a television signal in which the synchronization signal protrudes in the opposite direction to the imitation signal, that is, by the negative synchronization method, and Japan's current system, the NTSC system, also corresponds to this. Although this method makes it easy to separate the synchronization signal, it is disadvantageous in terms of signal-to-noise ratio since approximately 30% of the video signal dynamic range is used for the synchronization signal alone. Therefore, a positive polarity synchronization method has been proposed in which a synchronization signal as shown in Figure 6 (b) is added with the same polarity as the image signal. For example, this method has already been disclosed in Japanese Patent Application Laid-open No. 60-163577, ``Horizontal synchronization signal insertion method.'' However, in order to separate the synchronization signal from the video signal using this positive polarity synchronization method, it is not possible to separate the synchronization signal in the amplitude direction like the NTSC signal. Therefore, a frame synchronization signal with a special form as shown in FIG. The input video signal is phase-locked with the synchronization reproducing circuit of the television receiver by extracting the horizontal synchronization signal based on the obtained phase relationship. On the other hand, synchronized playback and signal processing of this image-reproduction signal are generally performed by digital signal processing, and it is necessary to perform analog-to-digital conversion (hereinafter referred to as A/D conversion); It is necessary to perform DC regeneration clamping. Therefore, in the above method, as shown in FIG. 7(a). As shown in (b), a clamp level period is inserted into the reflected signal as the median value of the signal dynamic range (value to be clamped). During this clamp level period, accurate DC reproduction can be performed by performing keyed clamping using a clamp pulse during a constant level period, such as a horizontal synchronizing signal. Figure 4 shows the A/D conversion circuit that performs this keyed clamp. 1 in the diagram
is a video signal input terminal; 2 is a clamp circuit into which the video signal is input; 3 is an A/D converter to which the output of the clamp circuit 2 is connected; 4 is an input terminal to which the output of the A/D converter 3 is connected. 6, a clamp level setting switch; 7, a clamp level detection circuit to which the output of the A/D converter 3, the output of the synchronous reproduction circuit 5, and the output of the clamp level setting switch 6 are connected; 8 is a D/A conversion circuit to which the output of the clamp level detection circuit 7 is input, and its output is connected to the clamp circuit 2. Note that one output of the synchronous regeneration circuit 5 is connected to the clamp circuit 2.
It is also supplied to Next, we will explain the operation. The clamp circuit 2 is configured as shown in FIG. 8, for example, and biases the DC potential applied as a clamp level to the input signal through a resistor T while the switch l2 is closed by a clamp pulse. be. This clamp pulse is generated by the synchronous regeneration circuit 5. On the other hand, the clamp level is given as the average value during the clamp level period of the difference from the clamp level setting value digitally set using the data of the clamp level period inserted into the video signal data. 4, and is clamped to output the value given by the clamp level setting switch 6 in a loop including the A/D converter 3 in FIG. By the way, in response to the recent demand for higher image quality in television programs, a new method has been proposed for the NTSC system that uses digital signal processing and is compatible with current television receivers. Therefore, it is thought that the need for A/D conversion of NTSC signals will increase in the future. Figure 5 shows the structure of an A/D conversion circuit that receives an NTSC system signal as input.The NTSC system does not have a clamp level period, as seen in the example of the positive polarity synchronization system signal mentioned above. The pedestal level at the front and rear porches of the horizontal synchronization signal is usually used as a reference for clamping. Figure 9 shows an example of setting the clamp level and clamp pulse within the A/D converter dynamic range. Problems to be Solved by the Invention As described above, in a digital signal processing circuit that receives different types of synchronization signals as input, a clamp circuit suitable for each synchronization signal must be provided, which increases the complexity of the circuit and increases costs. There was a problem in that it led to an increase in This invention was made in order to solve the above problem, and in a circuit that inputs image signals having different synchronization signals and performs A/D conversion, a video signal clamp circuit that can automatically respond to the synchronization signals is provided. The purpose is to obtain. Means for Solving the Problems The present invention provides a clamp operation in which the value of the clamp level period inserted in the vertical retrace period of a video signal is used as a reference voltage, and a reference voltage in which the basal level set in the horizontal synchronization signal period is used as the reference voltage. The clamp level reference value, the clamp level reference position, and the clamp pulse position are switched by a synchronization judgment circuit that determines which method is input for the clamp operation. Effect: In this invention, by virtue of the structure described above,
A single clamp circuit responds to input video signals with different synchronization signals and performs DC reproduction. EXAMPLE An example of the present invention will be explained below with reference to the drawings. FIG. 1 is a block diagram showing a clamp circuit according to an embodiment of the present invention. In the figure, 1 to 5, 7, and 8 are the same as the conventional circuit, and detailed explanation will be omitted. 22 is the synchronous playback a
23 is a clamp level switching circuit whose output terminal is connected to the clamp level detection circuit 7 and receives a switching signal from the synchronization judgment circuit 22; The output signal of the synchronization regeneration circuit 5 and the output signal of the synchronization determination circuit 22 are input, and the output thereof is applied to the clamp circuit 2 and the clamp level detection circuit 7.
This is a clamp control pulse generation circuit applied to the FIG. 2 is an explanatory waveform diagram showing the operation of this embodiment,
The same diagram (@ indicates the case where an NTSC signal is input as the input video signal. The synchronous reproducing circuit 5 in Figure 1 is capable of responding to each input signal, and oscillates at an oscillation frequency corresponding to the human input signal. The synchronization determination circuit 22 determines that the input signal is an NTSC signal from the synchronized signal frequency, for example, a horizontal frequency of 15.75 KHz. The clamp control pulse generator 11l124 outputs DC level sample pulses and pulses to the clamp level detection circuit 7. is tjlm as shown in Fig. 3. In the figure, the input reflection signal data is first subtracted from the clamp level setting value in the subtractor 13.
This clamp level setting value is switched in response to the input signal by the clamp level switching circuit 23 shown in FIG. Next, it is added to the output of the latch circuit 15 by the adder l4. As a result, the output of this latch circuit 15 is
This shows the cumulative difference between the DC level sample value and the clamp level setting value. Next, the clamp level is calculated by dividing this output by the output of the counter l6 indicating the number of samples using the divider 17. The clamp level data is latched by the latch circuit 18 and updated by a reset pulse generated by the clamp control pulse generating circuit 24 for each field. This clamp level data is converted into an analog quantity by the D/A converter 8, and added to the clamp pulse period input video to perform a clamp operation. On the other hand, in the imitation signal to which a positive synchronization signal is added,
For the camphor tree shown in Figure 2 (b), the clamp control pulse is generated 1 time.
24, the clamping operation is performed by arranging a plurality of DC level sample pulses in the clamp level period and taking the average of each data as the clamp level data. As described above, according to the clamp circuit according to the present invention,
For video signals with different synchronization signals, it is possible to automatically perform clamping corresponding to each signal, and in any case, the average value of multiple sample points is used as the clamp level, so a stable result can be obtained. have.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a television signal clamp circuit in one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation in one embodiment of the present invention, and FIG. 3 is a block diagram of a clamp level detection circuit. Block diagram showing the configuration, Figure 4. Figure 5 is a block diagram of a conventional clamp circuit, Figure 6 is a waveform diagram of a video signal using negative synchronization and positive synchronization signals, and Figure 7 is an example of a video signal format with positive synchronization added. FIG. 8 is a block diagram showing the structure of an analog lamp circuit, and FIG. 9 is an explanatory diagram showing examples of clamp positions and levels in positive polarity synchronization and negative polarity synchronization signals. l...Input terminal, 2...Analog clamp circuit, 3...A/D converter, 4...
・Output terminal, 5... Synchronous playback circuit, 7...
... Clamp level detection circuit, 8 ... D/A converter, l3 ... Subtractor, l4 ... Adder, l5 ... Latch circuit, l6... Counter circuit, 17... Division circuit, 18...
... Latch circuit, 22 ... Synchronization judgment circuit, 23
... Clamp level switching circuit, 24...
・Clamp control pulse generation circuit.

Claims (2)

[Claims] (1) An A/D converter that obtains digital video signal data from an analog video signal, an analog clamp circuit located upstream of the A/D converter, and an analog clamp circuit that obtains digital video signal data from the digital video signal data in phase synchronization with the video signal. A synchronous reproducing circuit capable of reproducing a horizontal synchronizing signal, a vertical synchronizing signal, and a clock pulse; a clamp level detecting circuit detecting a clamp level from the video signal data; and D converting output data of the clamp level detecting circuit into an analog signal. /
A clamp circuit comprising an A converter and feeding back the output of the D/A converter to the analog clamp circuit, comprising means for determining the format of the input video signal from the output of the synchronous reproducing circuit, and a means for determining the format of the input video signal from the output of the synchronous reproducing circuit, A clamp circuit comprising means for changing a reference position of a reference voltage of the clamp level detection circuit, a reference value for comparison with the reference voltage, and a position of a clamp pulse applied to the analog clamp circuit. (2) When an NTSC signal is input as the input video signal, select a position indicating the pedestal level during the horizontal synchronization period as the reference position for the clamp level, and calculate the clamp level from the average of these reference voltages in field units. A clamp circuit according to claim (1), characterized in that: