JPH05199427A - Vertical picture distortion correcting circuit - Google Patents

Abstract

PURPOSE:To eliminate discontinuous points of a vertical picture distortion correction signal to obtain a distortionless picture. CONSTITUTION:A vertical picture distortion correcting circuit 15 is provided with an interpolation data generating circuit 5 which generates interpolation data of a vertical fly-back blanking period based on vertical picture distortion correction data before and after the vertical fly-back blanking period and a switching circuit 6 which takes a vertical fly-back blanking signal as the input and switches vertical picture distortion correction data outputted from a waveform memory 1 and interpolation data outputted from the interpolation data generating circuit 5. In the vertical fly-back blanking period, interpolation data outputted from the interpolation data generating circuit 5 is inputted to a D/A conversion circuit 3 instead of vertical picture distortion correction data outputted from the waveform memory 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in a multi-frequency compatible display capable of correctly displaying an input video signal even if the horizontal deflection frequency and the vertical deflection frequency are different. The present invention relates to a vertical screen distortion correction circuit in a deflection control circuit.

[0002]

2. Description of the Related Art A conventional screen distortion correction circuit used for a display has a digital memory as described in Japanese Patent Laid-Open No. 64-12716, and reads various kinds of screen distortion correction data from the memory. Read the screen distortion correction data at the timing synchronized with the horizontal and vertical sync signals,
The analog / digital signal is converted by digital / analog conversion and then smoothed by a low pass filter to obtain a screen distortion correction signal such as a parabolic waveform.

[0003]

In the above-mentioned prior art, since the vertical screen distortion correction signal is created with reference to the vertical blanking signal, the vertical screen distortion correction signal is applied to the raster displaying the video signal. Only the line period is non-target. Therefore, as shown in FIGS. 4 and 3, at the start point of the correction waveform, a point where the correction waveform becomes discontinuous occurs, and this discontinuity causes the characteristics of the low-pass filter and the distortion correction waveform amplifier. Due to this, there was a problem that the upper part of the screen was locally distorted. Further, the problem is that when the correction waveform becomes asymmetric due to the adjustment of the vertical display position, the data difference at the discontinuous point increases, and the local distortion at the upper part of the screen also increases.

According to the present invention, instead of the vertical screen distortion correction data in the vertical blanking period, interpolation data interpolated from the vertical screen distortion correction data corresponding to before and after the vertical blanking period is used in the vertical blanking period. Thus, it is an object of the present invention to eliminate discontinuity points in the correction waveform and provide a screen without distortion even if the vertical display position is adjusted.

[0005]

A timing control circuit for generating and outputting an address and a timing control signal and vertical screen distortion correction data are stored, and
A waveform memory that receives an address and a timing control signal output from the timing control circuit, reads the vertical screen distortion correction data stored in a storage location corresponding to the address, and outputs the vertical screen distortion correction data according to the timing control signal. A vertical screen blanking correction circuit configured to perform digital / analog conversion of the vertical screen correction data output from the waveform memory and output as a vertical screen distortion correction signal. Of the vertical screen distortion correction data output from the waveform memory by inputting a signal,
An interpolation data generation circuit for creating interpolation data for a vertical blanking period based on vertical screen distortion correction data corresponding to before and after the vertical blanking period, and inputting the vertical blanking signal, from the waveform memory. A switching circuit for switching the output vertical screen distortion correction data and the interpolation data output from the interpolation data generation circuit is provided, and the digital / analog conversion circuit is provided with the waveform memory during a vertical blanking period. In place of the vertical screen distortion correction data output from, the interpolation data output from the interpolation data generating circuit is input.

[0006]

The interpolation data generating circuit creates the interpolation data from the vertical screen distortion correction data corresponding to before and after the vertical blanking period so that the vertical screen distortion correction signal continuously changes during the vertical blanking period. The switching circuit switches and outputs the interpolation data output from the interpolation data generation circuit in place of the vertical screen distortion correction data output from the waveform memory during the vertical blanking period. Then, the output vertical screen distortion correction data is digital / analog converted by the digital / analog conversion circuit and output as a vertical screen distortion correction signal.

Therefore, the vertical screen distortion correction data input to the digital / analog conversion circuit continuously changes during the vertical blanking period, and as a result, the vertical screen distortion output from the digital / analog conversion circuit. The correction signal will change continuously.

As a result, since the discontinuity points are removed from the waveform of the vertical screen distortion correction signal, the upper part of the screen is not locally distorted.

[0009]

EXAMPLE An example of the present invention will be described below with reference to FIG.

In FIG. 1, reference numeral 15 is a vertical screen distortion correction circuit, 1 is a waveform memory for storing screen distortion correction data obtained by digitizing a screen distortion correction signal, and 2 is a waveform memory 1 for obtaining necessary screen distortion correction data. In order to control the waveform memory 1, 3 is a digital / analog conversion circuit (hereinafter referred to as a D / A conversion circuit), 4 is an output port circuit, 5 is a vertical blanking period (hereinafter, V.B.
An interpolation data generation circuit for creating interpolation data for the LK period), and a switching circuit 6 for switching the screen distortion correction data output from the waveform memory 1 and the interpolation data output from the interpolation data generation circuit. FIG. 2 is a diagram showing the entire synchronous deflection control circuit including the vertical screen distortion correction circuit 15 of FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 14 is a synchronous deflection control circuit, 7 is a control circuit composed of a microcomputer (hereinafter referred to as CPU), 8 is a memory composed of a read-only memory and a readable / writable memory, and 9 is a CP.
Input-only port circuit for U7 interface,
Reference numeral 10 is an input / output port circuit, 11 is a synchronization processing circuit that performs processing related to synchronization such as separation of a synchronization signal from an input video signal, frequency detection of the synchronization signal, and polarity unification, 12 is an output-only port circuit, and 13 is D / A conversion. Circuit. In FIG. 2, C
The memory 7, the input-only port circuit 9, the input / output port circuit 10, the output-only port circuits 4 and 12, and the interpolation data generation circuit 5 centering on the PU 7 are mutually connected by an address bus, a data bus, and a control bus. And the timing control thereof. This operation is generally the same as the operation performed by the microcomputer for the peripheral circuits.

FIGS. 3 to 5 are explanatory views showing the operation state of the main part and the signal waveform of the main part of FIG.

The operation of this embodiment will be described below.

The waveform memory stores vertical screen distortion correction data corresponding to the absolute position of the cathode ray tube surface shown in FIG. The CPU 7 fetches information (horizontal frequency, vertical frequency, sync polarity, V.BLK period, etc.) that is processed by the synchronization processing circuit 11 from the input / output port circuit 10 and is necessary for identifying the input video signal, and based on these information. Then, the data required to control the screen size and position and the data required to correct the screen distortion are sent to the output dedicated port circuits 4 and 13. In the timing control circuit 2, the timing pulse H.S.C. synchronized with the data from the CPU 7, the system clock, the horizontal and vertical synchronizing signals. BLK, V.I. A timing control signal for determining an address and a read interval required for reading the screen distortion correction data is created by BLK. Further, the CPU 7 sets vertical screen distortion correction data corresponding to the vertical blanking period before and after the vertical blanking period from the waveform memory 1 (the vertical screen blanking correction data value before the vertical blanking period is A, and after the vertical blanking period). The vertical screen distortion correction data value of B) is taken in and the data necessary for generating the interpolation data is sent to the interpolation data generation circuit 5 based on these information. The interpolation data generation circuit uses the data from the CPU 7, the system clock, the V.V. Interpolation data (data that continuously changes between vertical screen distortion correction data A and B) necessary for the vertical blanking period is created by BLK. The switching circuit 6 uses the V. B
In the vertical blanking period based on the LK signal, the vertical screen distortion correction data output from the waveform memory 1 is replaced with the interpolation data output from the interpolation data generation circuit 5 and is supplied to the D / A conversion circuit 3. Through the above operation, the screen distortion correction data read from the waveform memory 1 and the interpolation data output from the interpolation data generation circuit 5 are converted into a screen distortion correction signal by the D / A conversion circuit 3. The waveform of the vertical screen distortion correction signal at this time is as shown in the correction waveform (3) of FIG.
At the start point (hereinafter referred to as a start point) of reading vertical screen distortion correction data from the waveform memory 1, a continuous waveform having no vertical screen distortion correction data difference is formed.

The correction waveform (1) in FIG. 3 and FIG. 4 are waveforms when the interpolation data is not switched in the conventional vertical blanking period, and the starter point is V. Since it is a rising edge (or an edge such as a falling edge) of the BLK signal, the waveform of the vertical screen distortion correction signal is asymmetric during the vertical blanking period,
There is a discontinuity at the start point. Furthermore, when the vertical display position is moved (The vertical display position adjustment uses a method of adjusting the raster position instead of adjusting the sync signal as in the horizontal position adjustment because the vertical blanking period is short. However, since the vertical screen distortion correction signal is a function of the absolute position of the cathode ray tube surface, the waveform of the vertical screen distortion correction signal has increased asymmetry like the correction waveform (1) shown in FIG. The waveform becomes a waveform, and the vertical screen distortion correction data difference at the discontinuous point becomes larger than that in FIG.

FIG. 6 is a block diagram showing a specific structure of the interpolation data generating circuit of FIG.

The interpolation data generation circuit 5 is a decoder / decoder that creates control signals necessary for fetching data sent from the CPU 7 from signals on the control bus and address bus.
Latch circuits 17, 18, 19 for latching data sent from the CPU 7 in accordance with control signals from the controller 16 and the decoder / controller 16; Differentiation circuit 20 that differentiates the BLK signal with the system clock to convert it to a start point signal, timing counter 22 that counts the system clock and outputs the count value, comparison that compares the data of the latch circuit 17 with the output of the timing counter 22 For the data whose frequency is divided by the frequency divider 21, the frequency divider 23 that determines the frequency division ratio based on the data of the latch circuit 18, and the clock output from the frequency divider 23, and whose count direction is controlled by the control signal output from the latch circuit 18. A counter 24, a data latch circuit 26 that latches the count value output from the data counter 24, and a clear control 25 that creates a CLR signal that initializes the timing counter from the signals output from the differentiating circuit 20 and the comparator 21 It is configured.

As described above, according to the present embodiment, the discontinuity point of the vertical screen distortion correction signal generated during the vertical blanking period is removed by the interpolation data generating circuit, and the vertical screen distortion correction signal continuously changes. Therefore, there is an effect that a screen without distortion can be obtained regardless of the characteristics of the low-pass filter and the distortion correction waveform amplifier.

[0018]

As described above, according to the present invention,
The vertical screen distortion correction signal discontinuity generated during the vertical blanking period can be removed by the interpolation data generation circuit so that the vertical screen distortion correction signal can be changed continuously. A screen without distortion can be obtained regardless of the characteristics of.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an entire synchronous deflection control circuit including the present invention.

FIG. 3 is a diagram showing a main part operating state and a main part signal waveform of FIG. 1;

FIG. 4 is a diagram similarly showing an operating state and a signal waveform.

FIG. 5 is a diagram similarly showing an operating state and a signal waveform.

FIG. 6 is a block diagram showing a specific configuration of the correction data generation circuit of FIG.

[Explanation of symbols]

1 ... Waveform memory, 2 ... Timing control circuit, 3
... D / A conversion circuit, 4 ... Output dedicated port circuit, 5 ... Interpolation data generation circuit, 6 ... Switching circuit, 7 ... CPU, 8 ...
Memory, 9 ... Input dedicated port circuit, 10 ... Input / output port circuit, 11 ... Synchronous processing circuit, 12 ... Output dedicated port circuit, 13 ... D / A conversion circuit.

Claims (1)

[Claims] 1. A timing control circuit for generating and outputting an address and a timing control signal, and vertical screen distortion correction data are stored, and the address and timing control signal output from the timing control circuit are input, A waveform memory for reading and outputting the vertical screen distortion correction data stored in a storage location corresponding to an address in accordance with the timing control signal, and digital / analog conversion of the vertical screen correction data output from the waveform memory. And a digital / analog conversion circuit for outputting a vertical screen distortion correction signal as a vertical screen distortion correction signal. The vertical screen distortion correction circuit corrects vertical distortion in the screen by the vertical screen distortion correction signal output from the digital / analog conversion circuit. Vertical blanking at Of the vertical screen distortion correction data output from the waveform memory, and creates interpolation data for the vertical blanking period based on the vertical screen distortion correction data corresponding to before and after the vertical blanking period. An interpolation data generating circuit for inputting the vertical blanking signal, and the vertical screen distortion correction data output from the waveform memory,
A switching circuit for switching between the interpolation data output from the interpolation data generation circuit is provided, and the digital / analog conversion circuit is provided with the vertical screen distortion correction data output from the waveform memory during a vertical blanking period. Instead, the vertical screen distortion correction circuit is characterized in that the interpolation data output from the interpolation data generation circuit is input.