JPH06311383A - Distortion correction circuit - Google Patents

Abstract

PURPOSE:To obtain a pattern without distortion by generating and inserting interpolation data between distortion correction data when the distortion correction data in a waveform memory are read so as to compensate insufficient smoothing by a low pass filter. CONSTITUTION:When distortion correction data in a waveform memory 1 are read, interpolation data outputted from an interpolation data generating circuit 5 are outputted in place of the distortion correction data outputted from the waveform memory 1 by a switching signal outputted from the interpolation data generating circuit 5. When a signal outputted from a changeover circuit 3 is D/A-converted and outputted as a distortion correction signal. Thus, a time or interval of distortion correction data inputted to a D/A converter circuit 3 is equal to or close to a time or an interval of distortion correction data stored in the waveform memory 1. Thus, insufficient smoothing by a low pass filter 7 is compensated by the distortion correction signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in a multi-frequency compatible display capable of correctly displaying an image signal even if the input image signal has a different horizontal deflection frequency or vertical deflection frequency. The present invention relates to a distortion correction circuit in a deflection control circuit.

[0002]

2. Description of the Related Art A conventional distortion correction circuit used in a display has a digital memory as described in Japanese Patent Laid-Open No. 12716/1989, and various screen distortion correction data are read out from the memory. Screen correction data is read at the timing synchronized with the horizontal and vertical sync signals, converted into an analog signal by digital / analog conversion, and then smoothed by a low-pass filter to obtain a screen distortion correction signal such as a parabolic waveform. Has become.

[0003]

According to the above-mentioned prior art, when distortion correction is performed at a cycle different from the cycle in which the distortion correction data in the waveform memory is stored, the interval or time of the correction data read from the waveform memory is changed. Correspond. That is, the distortion correction data in the waveform memory is read out by the timing control signal different from the timing control signal storing the distortion correction data in the waveform memory, and the distortion correction is performed. Therefore, as shown in FIG. 3, when correction is performed at a frequency lower than the frequency at which the distortion correction data in the waveform memory is stored, the time or interval between the distortion correction data and the distortion correction data becomes long, and smoothing by the low-pass filter becomes difficult. There is a problem that the distortion becomes insufficient and the distortion cannot be corrected sufficiently.

According to the present invention, when distortion correction is performed in a cycle different from the cycle in which the distortion correction data in the waveform memory is stored, interpolation data is created and inserted between the distortion correction data and the distortion correction data to artificially correct the distortion. By making the time or interval between the data and the interpolation data equal or close to the time or interval between the distortion correction data and the distortion correction data stored in the distortion correction data in the waveform memory, the lack of smoothness by the low-pass filter is compensated for and there is no distortion. The purpose is to provide a screen.

[0005]

A timing control circuit for generating and outputting an address and a timing control signal and distortion correction data are stored, and an address and a timing control signal output from the timing control circuit are input. A waveform memory for reading and outputting the distortion correction data stored in a storage location corresponding to the address in accordance with the timing control signal, and digital / analog conversion of the distortion correction data output from the waveform memory And a digital / analog conversion circuit for outputting as a distortion correction signal, the distortion in the waveform memory is changed by a timing control signal different from the timing control signal storing the distortion correction data in the waveform memory. Correction day And an interpolation data generation circuit that creates interpolation data between the distortion correction data and the distortion correction data, and the distortion correction data output from the waveform memory and the interpolation data output from the interpolation data generation circuit. A switching circuit for switching is provided, and interpolation data output from the interpolation data generation circuit is input to the digital / analog conversion circuit instead of the distortion correction data output from the waveform memory. .

[0006]

The interpolation data generating circuit creates the interpolation data from the distortion correction data output from the waveform memory and the distortion correction data before or after the distortion correction data. The switching circuit is
When the distortion correction data in the waveform memory is read by a timing control signal different from the timing control signal storing the distortion correction data in the waveform memory, it is output from the waveform memory by the switching signal output from the interpolation data generation circuit. Instead of the distortion correction data, the interpolation data output from the interpolation data generation circuit is switched and output. The signal output from the switching circuit is digital / analog converted by the digital / analog conversion circuit and output as a distortion correction signal.

Therefore, when the distortion correction data in the waveform memory is read by the timing control signal different from the timing control signal in which the distortion correction data in the waveform memory is stored, the distortion correction data input to the digital / analog conversion circuit is read. The time or interval of is equal to or close to the time or interval of the distortion correction data and the distortion correction data storing the distortion correction data in the waveform memory, and as a result, the distortion correction signal that compensates for insufficient smoothing by the low pass filter is generated. It will be input to the low-pass filter.

As a result, the waveform of the distortion correction signal is sufficiently smoothed, so that the distortion of the screen can be sufficiently corrected.

[0009]

EXAMPLE An example of the present invention will be described below with reference to FIG.

In FIG. 1, reference numeral 15 is a distortion correction circuit, 1 is a waveform memory for storing distortion correction data obtained by digitizing a distortion correction signal, and 2 is a waveform memory 1 for obtaining necessary distortion correction data from the waveform memory 1. Timing control circuit 3 for controlling a digital / analog conversion circuit (hereinafter referred to as a D / A conversion circuit), 4 an output port circuit, 5
Is a timing control signal different from the timing control signal storing the distortion correction data in the waveform memory 1, and when the distortion correction data in the waveform memory 1 is read out, the interpolation data is created between the distortion correction data and the distortion correction data. A data generation circuit, 6 is a switching circuit for switching between distortion correction data output from the waveform memory 1 and interpolation data output from the interpolation data generation circuit 5, and 7 is a distortion correction signal output from the D / A conversion circuit 3. It is a smoothing low-pass filter (hereinafter referred to as LPF). 2 is shown in FIG.
6 is a diagram showing an entire synchronous deflection control circuit including the distortion correction circuit 15 of FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 14 is a synchronous deflection control circuit, 8 is a control circuit (hereinafter referred to as a CPU) including a microcomputer, 9 is a memory including a read-only memory and a read / write memory, and 10 is a C
Input-only port circuit for interfacing PU8, 11 is an input / output port circuit, 12 is a synchronization processing circuit for performing processing related to synchronization such as separation of a synchronization signal from an input video signal, frequency detection of the synchronization signal, polarity unification, and 13 is an output Dedicated port, 16 is a D / A conversion circuit. In FIG. 2, C
The memory 9, the input-only port circuit 10, the input / output port circuit 11, the output-only port circuits 4 and 13, and the interpolation data generation circuit 5 centering on the PU are mutually information by an address bus, a data bus, and a control bus. And the timing control. This operation is generally the same as the operation performed by the microcomputer for the peripheral circuits.

FIGS. 3 to 4 are explanatory views showing the operation state of the main part and the signal waveform of the main part of FIG.

The operation of this embodiment will be described below.

The waveform memory 1 stores distortion correction data necessary for distortion correction. The CPU 8 fetches the information (horizontal frequency, vertical frequency, polarity of the synchronizing signal, horizontal and vertical blanking periods, etc.) processed by the synchronous processing circuit 12 from the input / output port circuit 11 and necessary for identifying the input video signal, Based on the information, output the data necessary for controlling the screen size and position and the data necessary for distortion correction. Dedicated port circuit 4,
Send to 13. In the timing control circuit 2, CP
A timing signal for determining an address and a read interval required for reading the distortion correction data according to the data from U8, the system clock, and the reference signal (2) (for example, the horizontal and vertical blanking signals) synchronized with the horizontal and vertical synchronizing signals. To create. Further, the CPU 8 determines whether the horizontal or vertical frequency is the same as the horizontal or vertical frequency in which the distortion correction data is stored in the waveform memory 1, and determines the determination result and the data necessary for generating the interpolation data. Send to 5. The interpolation data generation circuit 5 is based on the determination result from the CPU 8 and the data necessary for generating the interpolation data, the system clock, and the reference signal (1) synchronized with the horizontal and vertical synchronization signals (for example, horizontal and vertical blanking signals). The reference signal (2) supplied to the timing control circuit 2, the timing control signal to the waveform memory 1, the address signal, the control signal to the switching circuit 6 and the like, and the distortion correction data from the waveform memory 1 are input to create the interpolation data. Do.
The switching circuit 6 supplies the D / A conversion circuit 3 with the interpolation data output from the interpolation data generation circuit 5 instead of the distortion correction data output from the waveform memory 1 according to the control signal from the interpolation data generation circuit 5. Through the above operation, the distortion correction data read from the waveform memory 1 and the interpolation data output from the interpolation data generation circuit 5 are converted into a distortion correction signal by the D / A conversion circuit 3. When the distortion correction data in the waveform memory 1 is read by a timing control signal different from the timing control signal storing the distortion correction data in the waveform memory 1, the waveform of the distortion correction signal is the output of the D / A conversion circuit in FIG. As in the signal fb ′, a waveform is created by inserting interpolation data between the distortion correction data and the distortion correction data, and the distortion correction data in the waveform memory is stored at a pseudo time or interval between the distortion correction data and the interpolation data. The distortion correction data becomes equal to or close to the time or interval between the distortion correction data, and becomes a distortion correction signal that compensates for insufficient smoothing by the low-pass filter.

FIG. 5 is a block diagram showing a specific structure of the interpolation data generating circuit of FIG.

The interpolation data generation circuit 5 latches the distortion correction data from the decoder / controller 20 and the waveform memory 1 for generating the control signals necessary for fetching the data sent from the CPU 8 from the signals of the control bus and the address bus. A latch circuit 18, a latch circuit 21 for latching data sent from the CPU 8 in accordance with control signals from the decoder / controller 20, a system clock, and a reference signal (1) are input and supplied to the switching circuit 6 based on the data from the CPU 8. Switching signal, reference signal (2) supplied to timing control circuit 2, latch circuit 1
Timing circuit 1 for creating a latch signal for controlling 8
7. The arithmetic circuit 19 receives the output of the latch circuit 18 and the distortion correction data and creates interpolation data.

FIG. 6 is an explanatory diagram showing the operation states and operation signals of the main parts of FIG. 5, showing the operation when one point of interpolation data is inserted between the distortion correction data. CP
U8 fetches information (horizontal frequency, vertical frequency, polarity of synchronizing signal, horizontal and vertical blanking periods, etc.) processed by the synchronous processing circuit 12 from the input / output port circuit 11 and necessary for identifying the input video signal, and stores the waveform memory. It is determined whether or not the horizontal or vertical frequency is the same as the horizontal or vertical frequency in which the distortion correction data is stored in 1, and the determination result and the data necessary for generating the interpolation data are sent to the interpolation data generation circuit 5. The interpolation data generation circuit creates a control signal necessary for the decoder / controller 20 from the signals of the control bus and the address bus to capture the data sent from the CPU 8,
The data sent from U8 is taken into the latch circuit 21.
The latch circuit 21 sends the fetched data to the timing circuit 17. The timing circuit 17 advances the phase of the reference signal (1) by a half of the reading interval (time) and outputs it as the reference signal (2) when it is necessary to create the interpolation data according to the determination result of the CPU 8. Also, the timing circuit 1
Reference numeral 7 creates a latch signal and a switching signal that change in a cycle of half the read interval (time) and supplies them to the latch circuit 18 and the switching circuit 6. Timing control circuit 2
Also, the waveform memory 1 uses the reference signal (1) whose phase is advanced by half of the read interval (time).
Distortion correction data is output earlier by half the read interval (time). The latch circuit 18 latches the distortion correction data according to the latch signal and outputs the latched distortion correction data to the arithmetic circuit 19. The distortion correction data output from the latch circuit 18 becomes the distortion correction data synchronized with the reference signal (1). The arithmetic circuit 19 inputs the distortion correction data having different phases by half of the read interval (time), that is, the distortion correction data output from the waveform memory 1 and the distortion correction data output from the latch circuit 18, and reads the read interval (time). The correction data is created by adding the distortion correction data having a different phase by half and halving it. The switching circuit 6 inputs the interpolation data created by the arithmetic circuit 19, and outputs the interpolation data to the D / A conversion circuit instead of the distortion correction data output from the waveform memory 1 in response to the switching signal. As a result, D
The signal input to the A / A conversion circuit includes pseudo distortion correction data in which interpolation data is inserted between distortion correction data and distortion correction data in which the time or interval of the interpolation data stores the distortion correction data in the waveform memory. The signal becomes equal to or close to the time or interval of the distortion correction data. This operation is shown in FIG. Since the interpolation data output from the arithmetic circuit also includes the distortion correction data output from the waveform memory 1, a necessary distortion correction signal can be obtained even if the switching signal supplied to the switching circuit 6 is only on the interpolation data side.

If it is not necessary to create the interpolation data according to the determination result of the CPU 8, the timing circuit 17 outputs the reference signal (1) as it is as the reference signal (2). Further, the switching signal is limited to the distortion correction data output from the waveform memory.

In the above embodiment, one point of interpolation data is inserted between the distortion correction data and the distortion correction data. However, the number of insertions of the interpolation data is not limited, and the distortion correction data (interpolation data) and the interpolation data are not limited. The time or interval may be equal to or close to the time or interval between the distortion correction data stored in the waveform memory 1 and the distortion correction data.

As described above, according to this embodiment, the distortion correction data in the waveform memory 1 is changed by the timing control signal different from the timing control signal in which the distortion correction data in the waveform memory 1 is stored by the interpolation data generating circuit 5. When reading, the distortion correction data in which the interpolation data is created and inserted between the distortion correction data and the distortion correction data and the interpolation data are pseudo-stored in the waveform memory 1 Since it is equal to or close to the time or interval of the distortion correction data, there is an effect that a distortion correction signal that compensates for insufficient smoothing by the low pass filter can be obtained.

[0020]

As described above, according to the present invention,
When the distortion correction data in the waveform memory 1 is read by a timing control signal different from the timing control signal in which the distortion correction data in the waveform memory 1 is stored by the interpolation data generation circuit 5, when the distortion correction data is read between the distortion correction data and the distortion correction data. Interpolation data is created and inserted, and the time or interval between the distortion correction data and the interpolation data is pseudo or equal to or close to the time or interval between the distortion correction data and the distortion correction data stored in the waveform memory. It is possible to obtain a distortion correction signal that compensates for insufficient smoothing by the bandpass filter.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an entire synchronous deflection control circuit including the present invention.

FIG. 3 is an explanatory diagram showing an operation state of main parts and signal waveforms of main parts of FIG. 1;

FIG. 4 is an explanatory diagram showing an operation state of main parts and signal waveforms of main parts in FIG. 1;

5 is a block diagram showing a specific configuration of the interpolation data generating circuit of FIG.

FIG. 6 is an explanatory diagram showing an operation state of main parts and signal waveforms of main parts of FIG. 5;

[Explanation of symbols]

1 ... Waveform memory, 2 ... Timing control circuit, 3
... D / A conversion circuit, 4 ... Output dedicated port, 5 ... Interpolation data generation circuit, 6 ... Switching circuit, 7 ... Low pass filter, 8 ... CPU, 9 ... Memory, 10 ... Input dedicated port,
11 ... I / O port, 12 ... Synchronous processing circuit, 13 ... Output dedicated port, 14 ... Synchronous deflection control circuit, 15 ... Distortion correction circuit, 16 ... D / A conversion circuit, 17 ... Timing circuit, 1
8 ... Latch circuit, 19 ... Arithmetic circuit, 20 ... Decoder / controller circuit, 21 ... Latch circuit.

Claims (1)

[Claims] 1. A timing control circuit for generating and outputting an address and a timing control signal and distortion correction data are stored, and an address and a timing control signal output from the timing control circuit are input to the address. A waveform memory that reads and outputs the distortion correction data stored in a corresponding storage location according to the timing control signal, and a distortion correction by digital / analog converting the distortion correction data output from the waveform memory. A timing at which distortion correction data in the waveform memory is stored in a distortion correction circuit that is configured by a digital / analog conversion circuit that outputs as a signal, and that corrects distortion by the distortion correction signal output from the digital / analog conversion circuit. Ties different from control signal And the distortion correction data output from the waveform memory when generating the interpolation data between the distortion correction data and the distortion correction data when the distortion correction data in the waveform memory is read by the encoding control signal. And a switching circuit for switching between the interpolation data output from the interpolation data generation circuit, and the digital / analog conversion circuit is replaced by the interpolation data generation circuit instead of the distortion correction data output from the waveform memory. A distortion correction circuit characterized in that the output interpolation data is input.