JP2925271B2 - Synchronous signal separation device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal separation device for separating a synchronization signal in an image signal.

[Conventional technology]

Conventionally, there is a clamp circuit as a device for processing an image signal.

The clamp circuit forms a clamp pulse in synchronization with a composite synchronizing signal separated from the image signal, and clamps the image signal according to the formed clamp pulse.

[Problems to be solved by the invention]

The above-described clamp circuit can separate a complex synchronizing signal more accurate than the image signal if an accurate clamp process can be instantaneously performed on the image signal when the apparatus starts up. A clamp pulse is formed using the composite synchronization signal, and the clamp circuit operates normally.

However, if the image signal is not correctly clamped, the composite synchronization signal cannot be separated from the image signal, so that an accurate clamp pulse cannot be formed, and the clamp circuit cannot perform normal pulse clamp processing. There was a problem.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronous signal separating apparatus capable of quickly and accurately separating a synchronous signal from an image signal by performing a stable clamping process at all times.

[Means for solving the problem]

A synchronizing signal separating device according to the present invention is a device that separates a synchronizing signal in an image signal, the image signal being input, a clamp unit that clamps the input image signal, and an image signal clamped by the clamp unit. And a synchronizing signal separating unit for separating a synchronizing signal from the input image signal, and a continuous synchronizing unit in the clamping unit until the synchronizing signal is separated from the image signal supplied from the clamping unit in the synchronizing signal separating unit The clamping operation of the clamping means is controlled so that a typical clamping operation is performed, and after the synchronizing signal is separated from the image signal supplied from the clamping means in the synchronizing signal separating means, the clamping means The intermittent clamping operation is performed in synchronization with the synchronization signal separated by the synchronization signal separating means. In which a control means for controlling the clamping operation in the clamping means as is.

(Operation)

With the above-described configuration, the synchronization signal can be quickly and accurately separated from the image signal by always performing the stable clamping process.

〔Example〕

 Hereinafter, the present invention will be described with reference to examples of the present invention.

FIG. 1 is a diagram showing a schematic configuration when an embodiment of the present invention is applied to a playback device of a still video system.

In FIG. 1, a reproduced analog image signal reproduced from a magnetic disk (not shown) is supplied from an input terminal 1 to a clamp circuit 2, clamped by the clamp circuit 2, and digitized by an A / D converter 3. Output from the output terminal 4.

On the other hand, the digital image signal output from the A / D converter 3 is also supplied to a synchronizing signal separating circuit 5, where the synchronizing signal separating circuit 5 outputs a composite synchronizing signal (Csyn
c) is separated and supplied to the synchronization signal generator 6 at the next stage.

A PG pulse output from a PG coil (not shown) is supplied to the synchronization signal generator 6 via an input terminal 7 in synchronization with the rotation phase of the magnetic disk, and the synchronization signal generator 6 is supplied. Clamp pulse (Cp) and equalization pulse period detection signal (Ds) using composite synchronization signal and PG pulse (PG)
The clamp pulse is supplied to the terminal a of the changeover switch 8 and the equalization pulse period detection signal is supplied to the system controller 9.
To supply.

By the way, a predetermined voltage signal (Vcc) is supplied to the terminal b of the changeover switch 8 from the input terminal 10, and the system controller 9 uses the PG pulse and the equalization pulse period detection signal to generate an image in the clamp circuit 2. It is determined whether or not the signal is correctly clamped, and the clamp circuit 2 performs correct clamping by controlling the connection operation of the switching switch 6 according to the result of the determination.

 Hereinafter, the operation of the configuration shown in FIG. 1 will be described in detail.

FIG. 2 is a diagram showing a specific configuration example of an equalization pulse period detection signal generation circuit in the synchronization signal generation circuit 5 of FIG.
FIG. 3 is a timing chart showing signal waveforms of various parts in the configuration shown in FIG.

In FIG. 2, a composite synchronizing signal separated by the synchronizing signal separating circuit 5 (Csyn in FIG.
c) is synchronized with the rising edge (arrow in FIG. 3) of the horizontal synchronizing signal (Hsync) in the composite synchronizing signal by another circuit in the synchronizing signal generating circuit 6 at the input terminal 12, and the equalizing pulse Is formed and supplied.

In the still video system, each track on the magnetic disk is 7H ± from the position where the PG pulse is detected.
The image signal is recorded so that the rising edge of the vertical synchronizing signal in the image signal appears in the range of 3H (H is one horizontal scanning period).
After the edge of the pulse is detected, a rising edge of the horizontal synchronizing signal at the first H rises, and a P signal falling at the rising edge of the horizontal synchronizing signal at the 16th H is formed and supplied to the input terminal 13 in FIG. ing.

Further, a clock signal (CLK) for operating the equalizing pulse period detection signal generating circuit of FIG. 2 is supplied to an input terminal 15 of FIG. 2, and a synchronizing signal generating circuit is supplied to the input terminal 14 of FIG. A B signal which is at a high level for one clock period of the clock signal at the falling edge of the horizontal synchronizing signal in the composite synchronizing signal is formed and supplied by the other circuits in FIG.

In FIG. 2, the composite synchronizing signal, the A signal and the P signal inverted by the inverter 16 are supplied to an AND gate 17, which outputs an equalization pulse shown in FIG. It is supplied to the S terminal of the flip 18.

2, a B signal is supplied to a D terminal of the D flip-flop 19 and a clock signal is supplied to a CLK terminal of the D flip-flop 19. The edge detection signal (that is, the B signal) of the horizontal synchronizing signal is supplied from the D flip-flop 19 for one clock. C delayed for a period
A signal is output and supplied to the R terminal of the SR flip-flop 18.

A clock signal is supplied to CLK of the SR flip-flop 18, and the F signal shown in FIG. 3F and a signal obtained by inverting the F signal are AND-operated from the flip-flop 18.
It is supplied to gates 20 and 21.

The B signal is supplied to the AND gates 20 and 21. The G signal is output from the AND gate 20, and is supplied to the S terminal of the next-stage SR flip-flop 22.
The H signal is output from the gate 21 and the SR flip-flop is
It is supplied to 22 R terminals.

A clock signal is supplied to the CLK terminal of the SR flip-flop 22, and an equalizing pulse period detection signal (Ds in FIG. 3) is output from the SR flip-flop 22, and is output via an output terminal 23 in FIG. It is supplied to the system controller 9.

As described above, in this embodiment, the composite synchronization signal (Csync), 1/2
An equalizing pulse period detection signal (Ds) is formed from the H killer signal (A signal) and the edge detection signal (B signal) of the horizontal synchronizing signal. Since the signal is an essential signal in the digital signal processing circuit, and the configuration shown in FIG. 2 is also used for the skew compensation processing described later, the substantial increase in the circuit is very small.

If a normal clamping operation is performed in the clamp circuit 2 in FIG. 1 and the composite synchronizing signal is correctly separated in the synchronizing signal separating circuit 5, it is generated by the equalizing pulse period detection signal generating circuit shown in FIG. The equalization pulse period detection signal Ds
Since the falling edge of the composite synchronizing signal is present during the period of 7H ± 3H from the PG pulse as described above, the rising edge of the equalizing pulse period detection signal Ds (see FIG. X) exists during the period of 5H ± 3H from the PG pause, and the falling (Y in FIG. 3) exists during the period of 14H ± 3H from the PG pulse. Signal Ds
Is at a low level at 1H from the PG pulse, at a high level at 9H, and at a low level at 18H.

In the system controller 9 shown in FIG. 1, the equalization pulse period detection signal Ds supplied from the synchronization signal generator 6 at the preceding stage is set to the low level at the time of 1H from the PG pulse,
It is determined whether the condition of high level at the time of 9H and low level at the time of 18H are satisfied, and if so, the switching switch 8 of FIG. 1 is connected to the side a in FIG. If not satisfied, the switch 8 is connected to the side b in the figure.

That is, the switching switch 8 is connected to the system controller 9.
Is connected to the side a in the figure, the clamp pulse generated by the synchronizing signal generator 6 in the clamp circuit 2
When the clamp operation is performed in accordance with Cp and the switching switch 8 is connected to the side b in the drawing by the support of the system controller 9, the normal clamp operation is not performed in the clamp circuit 2 and the composite signal is output in the synchronous signal separation circuit 5. Since the synchronization signal is not correctly separated, the clamp circuit 2 performs a clamp operation in accordance with a predetermined voltage signal Vcc supplied from the input terminal 10, so that the image signal is transmitted to the next A / A in the clamp circuit 2. Accurate A / D conversion is performed in the D converter 3, and further, the synchronizing signal separating circuit 5 clamps to a clamp level such that a correct mixed synchronizing signal is separated.

As described above, according to the configuration described with reference to FIGS. 1 to 3, accurate clamp processing can be performed stably.

In the present embodiment, the timing chart shown in FIG. 3 shows a portion where the composite synchronization signal switches from the even field period to the odd field period. However, the timing chart shown in FIG. 3 shows a case where the composite synchronization signal switches from the odd field period to the even field period. The rising and falling of the equalization pulse period detection signal Ds become 1 / 2H earlier, but the determination condition in the system controller 9 does not change.

Further, in the present embodiment, a circuit for digitally separating the synchronization signal and the like has been described as an example. However, the present invention is also applicable to a circuit for performing analog separation.

Next, the operation when skew compensation is performed using the equalized pulse period detection signal Ds output from the synchronization signal generator 6 will be described with reference to FIG.

In a still video system, as is well known, field reproduction for repeatedly reproducing one field of an image signal recorded on a magnetic disk may be performed. In this field reproduction, an image is reproduced every one field period in order to interlace a reproduced image signal. The signal needs to be skew compensated.

The skew compensation is to form an odd field image signal from an odd field image signal or an odd field image signal from an even field image signal in order to form an odd field image signal every other field period. Are delayed by 1 / 2H with respect to the vertical synchronizing signal.

Incidentally, since the vertical synchronization signal is included in the equalization pulse period specified by the equalization pulse period detection signal Ds, skew compensation can be performed using the equalization pulse period detection signal Ds.

That is, as shown in FIG. 4, an I signal whose phase is inverted for each edge of the PG pulse is formed by flip-flop using a PG pulse (PG in the figure), and an equalizing pulse period is detected by an OR gate or the like. By ORing the signal Ds and the I signal, a J signal as shown in FIG. 4 is formed. The image signal is delayed by 1 / 2H while the J signal is at the low level, and is delayed during the high level. Skew compensation can be performed by outputting the signal as it is without 1 / 2H delay, and the composite synchronization signal after the skew compensation is as shown by Csync 'in FIG.

As described above, the equalization pulse period detection signal is a signal necessary even during skew compensation. Therefore, as described above, the clamp pulse is switched using this equalization pulse period detection signal, and accurate and stable. The configuration for performing the clamp operation can be realized without substantially increasing the circuit scale.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a synchronization signal separation device that can quickly and accurately separate a synchronization signal from an image signal by always performing a stable clamping process. become.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration when an embodiment of the present invention is applied to a playback device of a still video system. FIG. 2 is a diagram showing a specific configuration example of the equalization pulse period detection circuit in the synchronization signal generation circuit 5 of FIG. FIG. 3 is a timing chart showing signal waveforms of various parts in the configuration shown in FIG. FIG. 4 is a timing chart showing the operation at the time of skew compensation in the present invention. 1, 7, 10 ... input terminal 2 ... clamp circuit 3 ... A / D converter 4 ... output terminal 5 ... synchronization signal separation circuit 6 ... synchronization signal generator 9 ... system controller

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-175795 (JP, A) JP-A-1-289378 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/91-5/956 H04N 5/14-5/217

Claims (1)

(57) [Claims] 1. An apparatus for separating a synchronization signal in an image signal, comprising: a clamp means for inputting an image signal and clamping the input image signal; and an image signal clamped by the clamp means. Synchronizing signal separating means for separating a synchronizing signal from an input image signal; and a continuous clamping operation in the clamping means until the synchronizing signal is separated from the image signal supplied from the clamping means in the synchronizing signal separating means. Is performed so that the synchronizing signal is separated from the image signal supplied from the clamping means in the synchronizing signal separating means. The intermittent clamping operation is performed in synchronization with the synchronization signal separated by the separation means. Synchronizing signal separating apparatus characterized by comprising a control means for controlling the clamping operation in the lamp unit.