JP2517060B2 - Video signal processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for recording / reproducing image information and the like.

2. Description of the Related Art In recent years, video tape recorders (hereinafter referred to as VTRs) that process video signals using field memories have been commercialized. In VTRs, the field memory uses functions such as skew removal during fast-forward playback and rewind playback, and time base collector.These functions are the vertical and horizontal synchronization signals separated from the input video signal. It writes to the memory by, and the reading of the memory is done by the stable counter which has nothing to do with the sync signal. Therefore, the writing and reading of the memory become asynchronous,
When the digitally processed signal is switched to the original non-digitally processed input signal, the vertical synchronizing signal of the output video signal is disturbed and the screen vertically shakes.

An example of the above-described conventional video signal processing device will be described below with reference to the drawings.

FIG. 3 shows a block diagram of a conventional video signal processing apparatus for switching from a digital video signal to an input video signal in the case of a circuit configuration in which the input video signal is read asynchronously. In FIG. 3, 1 is an input terminal for video signals,
2 is an AD converter for converting the input video signal into a digital video signal, and 3 is at least 1
A memory that can store fields, 4 is a DA converter that converts digital video signals into digital-analog, 5 is a sync separation circuit that separates the input video signal into vertical sync signals and horizontal sync signals, and 6 is sync separation A write clock generation circuit that generates a block for controlling writing of the AD converter 2 and the memory 3 based on the signal output from the circuit 5, and 7 is a clock from the write clock generation circuit 6 and a sync separation circuit. A write address counter for generating a write address of the memory in accordance with a signal from 5, a memory 3 which is not synchronized with an input video signal.
And a read clock generation circuit that generates a clock for controlling the reading of the DA converter 4, 9 is a read address counter that generates a read address of the memory by a signal from the read clock generation circuit 8, and 10 is a high-level pulse. A switch for selecting an input video signal and switching the video signal digitally processed with a low-level pulse, a switching command generation circuit 11 for switching the switch 10, and a video signal output terminal 12.

The operation of the video signal processing apparatus configured to read data from the conventional memory asynchronously with the input video signal will be described with reference to FIG.

The video signal input from the input terminal 1 of FIG. 3 generates a clock for controlling the AD converter 2 memory 3 by the write clock generation circuit 6 with reference to the sync signal separated by the sync separation circuit 6. Let The write address generator 7 of the memory is operated by the signal of the write clock generation circuit 6 and the sync signal separated by the sync separation circuit 5 to generate the write address of the memory. The read address counter 9 is operated by the read clock generation circuit 8 that generates a clock for controlling the reading of the memory 3 and the DA converter 4 in synchronism with the input video signal, and the read address of the memory is generated. By the above control, the switching command generation circuit 11 switches the AD signal of the video signal, performs the desired processing in the memory 3 and then DA-converts the obtained digital video signal and the input video signal.
It is switched by the switch 10 and output from the output terminal 12.

However, the above-mentioned configuration has a problem that the screen is disturbed when switching is performed because the input video signal and the digital video signal are not synchronized.

In view of the above problems, the present invention provides a video signal processing device that solves the problem of the disturbance of the television screen when switching is performed by synchronizing the digital video signals that are not synchronized with the input video signal. It is provided.

Means for Solving the Problems In order to solve the above-mentioned problems, a video signal processing device of the present invention AD-converts an input video signal, and a writing standard created based on a vertical synchronizing signal separated from the video signal. The AD-converted signal is written to the memory capable of accumulating at least one field capacity by the write address counter preset to the memory start address by the signal, and is independent of the write reference signal, and an arbitrary number N (N is (Integer) When a horizontal sync signal address is counted, a read reference signal is generated, the read address counter preset to the memory start address reads from the memory, and the signal read from the memory is DA converted and DA converted video The video signal is being output by the selector switch between the signal and the input video signal. A video signal processing device, comprising: a time difference measuring circuit for measuring a time difference between the write reference signal and the read reference signal; and a read operation for setting the N value so that the time difference disappears according to an output result of the time difference measuring circuit. An address value setting circuit, and a switching signal control circuit that controls switching when the write reference signal and the read reference signal match in the time difference measurement circuit when switching from the DA conversion output signal to the input video signal Is.

Operation With the above-described configuration, the present invention eliminates the problem that the television screen is disturbed because the digital video signal that is not synchronized with the input video signal is switched after being synchronized with the input video signal. The video signal and the input video signal can be switched. Also, the digital processing is performed once before switching from the external input video signal to the video signal receiving the broadcast wave or before switching the channel of the television receiver, and by performing the above processing, the screen disturbance at channel switching is eliminated. .

Embodiment A video signal processing apparatus according to an embodiment of the present invention, which smoothly switches an input image signal and a digital image signal, will be described below with reference to the drawings.

FIG. 1 is a block diagram of a video signal processing device for smoothly switching an input image signal and a digital image signal according to an embodiment of the present invention. In FIG. 1, 21
Is an input terminal for a video signal, 22 is an AD converter for analog-digital converting the input video signal into a digital video signal, 23 is a memory capable of accumulating at least one field, 24 is a digital video signal as a video signal DA converter for digital-analog conversion, 25 is a sync separation circuit for separating the input video signal into a vertical sync signal and a horizontal sync signal, and 26 is an AD converter based on the signal output from the sync separation circuit 25. And a write clock generation circuit for generating a clock for controlling writing of the memory 23, 27
Is a write address counter that generates a write address of the memory by a write reference signal generated based on the vertical synchronizing signal separated by the sync separating circuit 25 and a signal from the write clock generating circuit 26.

28 is a read clock generation circuit that generates a clock for controlling the reading of the memory 23 and the DA converter 24 without synchronizing with the input video signal, and 29 is a read address of the memory according to the signal from the read clock generation circuit 28. Is generated, and an arbitrary number N (the value of N is 260,26 in the case of NTSC method)
It is a read address counter that generates a read reference signal when counting the addresses of horizontal synchronization signals of about 1,262,263). Reference numeral 30 is a time difference measuring circuit that measures the time difference between the write reference signal generated based on the vertical synchronizing signal separated by the sync separating circuit 25 and the read reference signal output from the read address counter 29.

31 is a switching command generation circuit that commands switching between the output signal and the input signal from the DA converter, 32 is a read address counter until the switching command generation circuit 31 outputs a switching command.
When the write reference signal and the read reference signal have a time difference in the time difference measuring circuit 31 after the switch command generating circuit 31 outputs the switch command, the arbitrary value N of the read address counter 29 is maintained. A read address value setting circuit for gradually matching the write reference signal and the read reference signal by changing the value N, 33 is a switch command generation circuit 31, a switch command is output, and the time difference measuring circuit 30 is a write reference signal. A switching signal generation circuit 34 that generates a switching signal between the output signal and the input signal of the DA converter when the signal and the read reference signal match is a switch that switches between the output signal and the input signal of the DA converter, and 35 is an output terminal. .

The operation of the video signal processing apparatus configured as described above will be described below with reference to FIGS. 1 and 2.

FIG. 2 shows the time difference between the write reference signal and the read reference signal, which is created based on the vertical synchronizing signal synchronized with the input video signal, and the signal for controlling the changeover switch between the input signal and the output signal from the DA converter. FIG. 6 is a timing diagram showing. (A) is a switching command of the output signal and the input signal of the DA converter output by the switching command generation circuit 31, and the low level is DA.
Output signal of the converter, High level is the input signal,
(B) is a write reference signal, (c) is a read reference signal, (d) is a signal output from the time difference measuring circuit 30 when the write reference signal and the read reference signal match,
(E) is a signal output from the switching signal control circuit 33, from t ₀ to
t ₄ represents the time difference between the write reference signal and the read reference signal.

In FIG. 1, a video signal input from an input terminal 21 is generated by a write clock generation circuit 26 by a write reference signal generated based on a vertical sync signal separated by a sync signal separation circuit 25, and an AD converter is produced. After being converted into a digital signal at 22, a write reference signal and a write clock generating circuit 26 generate an address from a write address counter 27 and write the address in the memory 23. When reading from the memory 23, the read address counter 27 has an arbitrary number N (the value of N is 26 in the case of the NTSC system regardless of the write reference signal).
About 0,261,262,263 is good, but the operation is the same for 250,275, etc.) When a horizontal sync signal address is counted, a read reference signal is generated, and a read address counter 29 and a read clock are preset to the start address of the memory 23. The circuit 28 reads from the memory 23, and the memory read signal is converted into an analog signal by the DA converter 24. When switching the DA converted video signal and the input video signal with the switch 34 to output the video signal,
The time difference measuring circuit 30 controls the read address value setting circuit 32 so as to reduce the time difference between the write reference signal and the read reference signal, and the read address counter 29 outputs N.
When the time difference disappears, a signal is sent to the switching signal control circuit 33 to switch the switch 34.

In FIG. 2, when the write reference signal of waveform (b) and the read reference signal of waveform (c) are digitally processed, there is a time difference such as t ₀ and t ₁ , but the switching command generation circuit 31 ( After the command like a) is output,
The time difference between the write reference signal and the read reference signal is made small like t ₂ , t ₃ and t ₄ so that they match. For example,
If the time difference is large when the arbitrarily set value is 262, the value of the read address value setting circuit 31 is set to 260 and is fed back to the read address counter 29, so that t ₂ and t ₃ of the waveform (b) are obtained. Address value setting circuit when the write reference signal suddenly approaches and the time difference becomes small
By controlling the value of 31 to 262 and feeding it back to the read address counter 29, control is performed to gradually match, and when the write reference signal and the read reference signal match, the time difference measurement circuit 30 outputs a low-level pulse as shown in the waveform (d). Is output. That is, even if a command for switching the output signal of the DA converter to the input signal is output from the switching command generation circuit 31, unless the time difference measurement circuit 30 outputs a low-level signal such as the waveform (d), the switching signal control circuit 33 outputs the signal. Does not output the signal (e) for controlling the changeover switch 34 for switching the output signal and the input signal of the DA converter. Switching signal control circuit
When the signal is output from 33, the selector switch 34
And the input signal or the output signal of the DA converter is output from the output terminal.

Further, the time difference measuring circuit 30, the switching command generating circuit 31, the read address value setting circuit 32, and the switching signal control circuit 33 can be easily implemented by a microcomputer.

As described above, according to the present embodiment, it is possible to solve the problem that the screen is disturbed when switching the signal that is not synchronized with the input video signal, and it is possible to switch quickly and smoothly.

EFFECTS OF THE INVENTION As described above, according to the present invention, a digital video signal that is not synchronized with an input video signal is switched in synchronization with the input video signal, so that switching can be performed quickly and smoothly. . Also, by performing digital processing once before switching the video signal from the external input video signal to the video signal receiving the broadcast wave or before switching the channel of the television receiver, by performing the above processing,
The screen is not disturbed when switching channels, and the screen can be switched smoothly.

[Brief description of drawings]

FIG. 1 is a block diagram of a video signal processing device according to an embodiment of the present invention, FIG. 2 is a timing diagram showing an output waveform of a switching signal control circuit, and FIG. 3 is a block diagram of a video signal processing device having a conventional configuration. Is. 21 …… input terminal, 22 …… AD converter, 23 …… memory, 24…
… DA converter, 25 …… Sync separation circuit, 26 …… Write clock generation circuit, 27 …… Write address counter, 28…
... Read clock generator circuit, 29 ... Read address counter, 30 ... Time difference measuring circuit, 31 ... Switching command generator circuit, 32 ... Read address value setting circuit, 33 ... Switching signal control circuit, 34 ... Switch, 35 …… Output terminal.

Claims (2)

(57) [Claims] 1. A capacity of at least one field by a write address counter which AD-converts an input video signal and presets a memory start address by a write reference signal generated based on a vertical synchronizing signal separated from the video signal. The AD converted signal is written in a memory capable of accumulating data, and the read reference signal is generated when the address of an arbitrary number N (N is an integer) of horizontal synchronizing signals is counted regardless of the write reference signal. A video signal processing in which a signal read from the memory is read by a read address counter preset to the memory start address, the signal read from the memory is DA-converted, and the DA-converted video signal and the input video signal are output by a changeover switch. A device, comprising: the write reference signal and the read reference signal A time difference measuring circuit for measuring a time difference, a read address value setting circuit for setting the value of N so as to eliminate the time difference according to an output result of the time difference measuring circuit, and a DA conversion output signal for switching to the input video signal. At this time, the video signal processing device is provided with a switching signal control circuit which controls to switch when the write reference signal and the read reference signal match in the time difference measuring circuit. 2. The video signal processing apparatus according to claim 1, wherein the write reference signal is output several H (H is a horizontal sync signal) before the vertical sync signal of the input video signal.