JPH0346619Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a video signal storage device, which allows the writing timing to the memory and the reading timing from the memory to be the same, thereby accurately reproducing images even with video signals having variations in the horizontal scanning period. I can do it,
Moreover, it is an object of the present invention to provide a video signal storage device that can accurately reproduce colors.

When playing back a recorded magnetic tape at variable speeds, the playback signal is output at a sufficient level and written to the video field memory, while the playback signal is not output at a sufficient level and is written into the video field memory. - A possible method is to read out the signal corresponding to the previous field written in memory and synthesize a high-quality screen without noise bars on the reproduced screen. In this case, there must be a correspondence between the memory address and the screen. Therefore,
It is common to allocate memory addresses based on the horizontal synchronization signal of the video signal.

However, the horizontal scanning period of a reproduced signal reproduced by a VTR or the like is not constant and always fluctuates, albeit slightly. Therefore, when writing a video signal to the memory and reading it out in the above-mentioned variable speed playback, etc., if the writing timing and the reading timing do not match based on the horizontal synchronization signal at the time of writing, the written signal The screen does not correspond to the screen based on the read signal, and a complete reproduced screen cannot be obtained. In particular, if the memory address is updated at a constant cycle determined by a theoretical value while ignoring the timing of the horizontal synchronization signal during writing, the phase of the color subcarrier will shift for each horizontal synchronization signal, making it impossible to perform accurate color reproduction.

This invention was made in view of the above facts,
Hereinafter, one embodiment will be described with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of a video signal storage device according to the present invention. First, the write mode will be explained. VTR that entered terminal 1
The reproduced composite video signal from the above is converted into a digital signal by an AD converter 2, while being separated into a horizontal synchronization signal and a vertical synchronization signal by a synchronization signal separation circuit 3. For example, the separated horizontal synchronizing signal a (FIG. 2A) is converted into a pilot signal b by the control signal generator 4.
(B in the same figure), and is also supplied to the switching signal generator 5 to be used as a switching signal. The control signal generator 4 includes a pilot signal generator 4a and an address control signal generator 4b.

The switch S is configured such that its movable contact piece is connected to terminal ``only'' when a switching signal is generated, and connected to terminal ``d'' during other periods. This allows for example video and video files configured with RAM etc.
The digital composite video signal from the AD converter 2 is written into the field memory 6 via terminal A of the switch S, while the pilot signal b from the control signal generator 4 is written only during the initial period of generation of the horizontal synchronizing signal a. It is written next to the composite video signal via terminal RO of switch S. The pilot signal b shown in FIG. 2B is expressed in analog form for convenience, but in reality, the pilot signal b is stored in the memory 6 as digital data. In the memory 6, 6a is a data input terminal, 6b is an address signal input terminal, and 6c is a read data output terminal.

When the writing of the pilot signal b is completed, the control signal generator 4 outputs the vertical address update control signal.
c ₁ (C in the same figure) is taken out and supplied to the memory 6,
As a result, the vertical address of the memory 6 is updated to prepare for writing the composite video signal in the next horizontal scanning period. In this way, when the writing of the composite video signal for one horizontal scanning period is completed, the pilot signal b is written, and then the vertical address is updated and the composite video signal for the next horizontal scanning period is written in the area of this updated address. The operation of writing the video signal is repeated to store one field of the video signal in memory.

On the other hand, the vertical synchronization signal separated by the synchronization signal separation circuit 3 is supplied to the switching signal generator 5 and the control signal generator 4, and the pilot signal is taken out and written next to the video signal of one field. A directional address update control signal _C2 is taken out to update the vertical address of the memory. As a result, when the memory 6 stores one field's worth of video signals, the vertical address is updated by the vertical synchronizing signal to prepare for writing the video signal in the horizontal scanning period at the beginning of the next field.

Next, the read mode will be explained. The memory 6 performs a read operation based on a read clock from a clock generator (not shown), but as it is, the written video signal is simply read out continuously regardless of the horizontal scanning period; The timing and read timing do not match with respect to the horizontal synchronization signal. Therefore, in the present invention, the vertical address of the memory is updated in accordance with the writing timing based on the pilot signal written during reading and writing, and the composite video signal is read out at the same timing as the writing timing. .

The composite video signal and pilot signal read out from the memory 6 are taken out from the output terminal 7, only the composite video signal is separated, DA converted, and supplied to a CRT etc. for image reproduction, while the composite video signal and pilot signal are The signal is supplied to the control signal generator 4, and the value of the digital data corresponding to the pilot signal, that is, the pattern of the digital data is detected, whereby only the pilot signal is separated. The control signal generator 4 is controlled by this pilot signal.
The vertical address update control signal C ₂ is taken out from the memory 6 and supplied to the memory 6, and the memory 6 has its vertical address updated by the vertical address update control signal C ₂ in preparation for reading in the next horizontal scanning period.

That is, in the memory 6, the vertical address is updated by reading out the pilot signal written at the time of writing, and the composite video signal written in the area of that address is read out, and this operation is repeated until 1. The field's composite video signal is read out with reference to the horizontal synchronization signal.

In this way, since the signal for the next horizontal scanning period is read out based on the pilot signal written at the time of writing, the read timing can be made to match the write timing based on the horizontal synchronizing signal. As a result, when a composite video signal with variations in the horizontal scanning period is written, it can be read out according to the variations, and therefore the screen and the memory 6 according to the reproduced composite video signal written in the memory 6 can be read out according to the variations.
The screen corresponds to the composite video signal read out from the screen.

Note that the separation of the synchronization signals is not limited to being performed before converting the composite video signal to a digital signal as in the above embodiment, but may be performed after converting the composite video signal to a digital signal.

Furthermore, the memory is not limited to field memory, but frame memory may also be used.

As described above, the video signal storage device according to the present invention includes an AD converter that AD converts an incoming video signal, a sync signal separation circuit that separates horizontal and vertical sync signals from the video signal, and a sync signal separation circuit that separates horizontal and vertical sync signals from the video signal. a switching signal generator that generates a switching signal within a generation period of the horizontal and vertical synchronizing signals in synchronization with the horizontal and vertical synchronizing signals supplied from a circuit; and a switching signal generator that generates a switching signal within a generation period of the horizontal and vertical synchronizing signals, and a switching signal supplied from the synchronizing signal separation circuit in a write mode. A pilot signal generator generates a pilot signal only during the initial period of generation of the horizontal and vertical synchronizing signals, and in the write mode, after the pilot signal is output from the pilot signal generator, an address update control signal is generated, and in the read mode a control signal generation circuit comprising an address control signal generator that generates an address update control signal after being supplied with a pilot signal read from the memory circuit; and a second input terminal and an output terminal to which the pilot signal is supplied from the control signal generation circuit, and in the write mode, the switching signal is supplied from the switching signal generation circuit only during the period when the switching signal is supplied from the switching signal generation circuit. A switch circuit connects the second input terminal and the output terminal, and during a period when the switching signal is not supplied, connects the first input terminal and the output terminal, and outputs an output signal from the switch circuit. a data input terminal to which the address update control signal is supplied, an address signal input terminal to which the address update control signal is supplied from the control signal generation circuit, and a read data output terminal, and updates the address in accordance with the address update control signal. The memory circuit is configured to write the output signal of the switch circuit, and in the read mode, updates the address in accordance with the address update control signal and outputs the written data from the read data output terminal. At the time of reading, the read timing can be made to match the write timing based on the synchronization signal.
If a video signal with variations in the horizontal scanning period, such as a reproduced signal such as In particular, the position of the color subcarrier with respect to the horizontal synchronization signal can always be made to correspond to an accurate position, and accurate color reproduction can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of one embodiment of the device of the present invention, and FIGS. 2A to 2C are signal waveform diagrams for explaining the operation of the device of the present invention. DESCRIPTION OF SYMBOLS 1... Composite video signal input terminal, 2... AD converter, 3... Synchronization signal separation circuit, 4... Control signal generator, 4a... Pilot signal generator, 4b...
... Address control signal generator, 5 ... Switching signal generator, 6 ... Video field memory, 6a ... Data input terminal, 6b ... Address signal input terminal, 6c ... Read data output terminal,
7...Output terminal, S...Switch.

Claims (1)

[Claims for Utility Model Registration] An AD converter for AD converting an incoming video signal; a sync signal separation circuit for separating horizontal and vertical sync signals from the video signal; a switching signal generator that generates a switching signal within a generation period of the horizontal and vertical synchronization signals in synchronization with the horizontal and vertical synchronization signals; and the horizontal and vertical synchronization signals supplied from the synchronization signal separation circuit in a write mode. A pilot signal generator generates a pilot signal only during the initial period of generation, and in a write mode, after the pilot signal is output from the pilot signal generator, an address update control signal is generated, and in a read mode, the address update control signal is read from the memory circuit. a control signal generation circuit comprising: an address control signal generator that generates an address update control signal after being supplied with a pilot signal; a first input terminal to which an output signal of the AD converter is supplied; It has a second input terminal and an output terminal to which the pilot signal is supplied from the control signal generation circuit, and in the write mode, the second input terminal and the output terminal are connected only during the period when the switching signal is supplied from the switching signal generation circuit. a switch circuit that connects the first input terminal to the output terminal and connects the first input terminal and the output terminal during a period when the switching signal is not supplied; and a data input to which the output signal is supplied from the switch circuit. a terminal, an address signal input terminal to which the address update control signal is supplied from the control signal generation circuit, and a read data output terminal, which updates the address in accordance with the address update control signal and outputs the switch circuit. A video signal storage device comprising a memory circuit in which a signal is written, and in a read mode, an address is updated in accordance with the address update control signal and the written data is output from the read data output terminal.