JP2659973B2 - Information signal processing circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information signal processing device for processing a video information signal having a synchronization signal including a vertical blanking period.

[Conventional technology]

As a device for recording an information signal, recently, a still image signal is recorded on a disk-shaped magnetic recording medium by a magnetic head or the like,
A still video recording / reproducing apparatus for reproducing this is beginning to appear.

FIG. 2 is a diagram showing a configuration example of a still video recording / reproducing apparatus.

In FIG. 2, during recording, a switch 6 is connected to the R side in the figure by an instruction of a system controller (not shown), the magnetic sheet 8 is rotated at a field cycle by a motor, and the magnetic head 7 is moved by a head (not shown). The mechanism is moved to a position on the magnetic sheet 8 specified by the system controller.

Then, the still image signal for one field inputted from the input terminal 1 is clamped by the clamp circuit 2 at, for example, a sync tip level, a predetermined emphasis is performed in the emphasis circuit 3, and the high frequency distribution is emphasized. After that, the signal is FM-modulated by the FM modulator 4, amplified by the recording amplifier 5, supplied to the magnetic head 7 via the switch 6 connected to the R side in FIG. Be recorded.

As described above, the magnetic sheet 8 is rotated at a field cycle by the motor 9, and the magnetic head 7 is movable in the radial direction of the magnetic sheet 8 by a head moving mechanism (not shown). In FIG. 8, a still image signal corresponding to, for example, one field per sheet is recorded by the recording operation described above.
Fields can be recorded.

Next, at the time of reproduction, the switch 6 is connected to the P side in the figure by an instruction of a system controller (not shown), the magnetic sheet 8 is rotated at a field cycle by a motor 9, and the magnetic head 7 is moved by a head (not shown). By mechanism
It is moved to a position on the magnetic sheet 8 designated by the system controller.

Next, the reproduction signal reproduced by the magnetic head 7 is supplied to the reproduction amplifier 10 via the switch 6 connected to the P side in the figure as described above, and after being amplified there, the FM demodulator The signal is demodulated at 11 and is subjected to de-emphasis having characteristics opposite to those at the time of recording in the de-emphasis circuit 12, and is supplied to a synchronization signal separation circuit 13 and an image signal separation circuit 14.

The synchronizing signal separating circuit 13 separates the horizontal and vertical synchronizing signals from the signal output by the de-emphasis circuit.
The horizontal and vertical synchronizing signals are output from an output terminal 16 and the image signals are output from an output terminal 15.
Output.

In addition, there are applications such as printing out a still image signal reproduced from the still video recording / reproducing device using a printer device and transmitting the image using a telephone line or the like. It is necessary to temporarily store the image signal in storage means such as a memory circuit.

FIG. 3 is a diagram showing a schematic configuration of a still image signal storage device used in the above case.

In FIG. 3, the horizontal and vertical synchronizing signals output from the output terminal 15 shown in FIG.
The image signal output from the output terminal 16 shown in FIG. 2 is supplied to the input terminal 18 shown in FIG.

Further, a freeze instruction signal is supplied to the input terminal 35 from a system controller (not shown). The freeze instruction signal is at a high (H) level when an image signal is written to the memory, and is at a low (L) level when the image signal is read from the memory.

The synchronization signal input from the input terminal 17 via the switch 32 is a clamp circuit 29, a monomultivibrator 22, a 1 / 2H
The killer circuit 20 is supplied to the vertical synchronization signal separation circuit.

The mono vibrator 22 includes a NAND gate 23 and a delay circuit 24.
And a gated oscillator circuit, and a sampling pulse synchronized with an edge before a horizontal synchronizing pulse of a synchronizing signal supplied to the monomultivibrator 22.
Output from ND gate 23, analog digital (A / D)
The data is supplied to a conversion circuit 30, a column address counter 25, a row address counter 26, a memory control circuit 28, and a digital / analog (D / A) conversion circuit 34.

Further, the horizontal synchronization signal is separated from the synchronization signal supplied by the 1 / 2H killer circuit 20, supplied to the column address counter 25, the row address counter 26, the memory control circuit 28, and supplied by the vertical synchronization signal separation circuit 21. The vertical synchronization signal separated from the synchronization signal is supplied to the row address counter 26,
It is supplied to the memory control circuit 28.

The operation of the still image signal storage device shown in FIG. 3 when writing an image signal will be described below.

When writing an image signal, an H level freeze instruction signal is output from the system controller (not shown) via the input terminal 35 to the switch 32 and the memory control circuit as described above.
28, the switch 32 is connected to the H side in the drawing, and various signals formed as described above are supplied to respective circuits from the synchronization signal supplied to the input terminal 17.

On the other hand, the image signal input from the input terminal 18 is input to the A / D conversion circuit 30 at a timing synchronized with the synchronization signal supplied in the clamp circuit 29, for example, after the sing chip portion is clamped to a predetermined DC level. The image signal is sampled in synchronization with the sampling pulse formed by the gated oscillator circuit,
One sample is converted into, for example, 8-bit digital data and supplied to the memory 31.

On the other hand, the column address counter 25 has a sampling pulse from the gated oscillator circuit and a 1 / 2H killer circuit.
The horizontal synchronization signal is supplied from 20, and the number of pulses is reset each time a pulse of the supplied sampling pulse is input and reset at a previous edge of the supplied horizontal synchronization signal. Is output to the switching circuit 27 as column address data.

Also, the row address counter 26 has the 1 / 2H killer circuit.
A horizontal synchronization signal is supplied from 20 and a vertical synchronization signal is supplied from a vertical synchronization signal separation circuit 21. Each time a reset pulse is reset by the supplied vertical synchronization signal and a synchronization pulse of the supplied horizontal synchronization signal is inputted, Count the number of pulses,
The count value is output to the switching circuit 27 as row address data.

As described above, the freeze control signal, the horizontal synchronization signal, the vertical synchronization signal, and the sampling pulse are supplied to the memory control circuit 28. Since the supplied freeze control signal is at the H level,
Reference numeral 28 outputs an H level write enable signal WE to the memory 31 for one field period in synchronism with the supplied vertical synchronizing signal, and puts the memory 31 in a data writable state.

The memory control circuit 28 outputs a horizontal synchronizing signal supplied during the period in which the H-level write enable signal WE is being output, a switching control signal SC of the switching circuit 27 and a row address set signal RAS at a timing synchronized with the sampling pulse. , A column address set signal CAS is output to the switching circuit 27 or the memory 31 to designate a write address on the memory 31, and the A / D conversion circuit 30 supplies one field supplied to the memory 31 as described above. The image data is written into the memory 31.

That is, the memory control circuit 28 outputs the RAS to the memory 31 at the timing when the horizontal synchronization pulse is input, and switches the switching circuit 27 so that the row address data output from the row address counter 26 is output to the memory 31. To
Control is performed by the SC, and a write row address on the memory 31 is specified. Further, the memory control circuit 28 outputs CAS to the memory 31 at the timing when the sampling pulse is input, and controls the switching circuit 27 so that the column address data output from the column address counter 25 is output to the memory 31. Control is performed by the SC, and a write column address on the memory 31 is specified.

Next, an operation of reading an image signal in the still image signal storage device shown in FIG. 3 will be described.

At the time of reading the image signal, an L level freeze instruction signal is supplied from the system controller to the switch 32 and the memory control circuit 28 via the input terminal 35 as described above, and the switch 32 is connected to the L side in the figure. A synchronization signal is output from the synchronization signal generation circuit 33 through the switch 32,
Various signals formed as described above from the synchronization signal are supplied to the respective circuits.

The freeze control signal, the horizontal synchronization signal, the vertical synchronization signal, and the sampling pulse are supplied to the memory control circuit 28, and the supplied freeze control signal is at the L level. A write enable signal WE is output to the memory 31, and the memory 31 is set to a data readable state.

During the period in which the write enable signal WE at the L level is being output, the memory control circuit 28 controls the switching control signal SC and the row address set signal of the switching circuit 27 at the timing synchronized with the supplied horizontal synchronizing signal and sampling pulse. The RAS and the column address set signal CAS are output to the switching circuit 27 or the memory 31 to designate a read address on the memory 31, read out the image data stored in the memory 31, and supply it to the D / A conversion circuit 34 .

The sampling pulse is supplied to the D / A conversion circuit 34.In synchronization with the sampling pulse, the supplied image data is D / A converted and converted into an analog image signal. Output more.

[Problems to be Solved by the Invention] In the still video recording / reproducing apparatus shown in FIG. 2, the waveform of the reproduced image signal output by the de-emphasis circuit at the time of reproduction is as shown in FIG. 4 (a).
Here, for simplicity of description, it is assumed that the reproduced image signal is composed of only the luminance signal component.

Figure 4 reproduced image signal as shown in a) includes a random noise, Figure 4 b _1, especially in the horizontal synchronizing signal portion), b
_As can be seen by comparing the portion A shown in ₂ ), different distortions occur in each horizontal scanning period. FIG. 4 b ₁ ) shows the waveform of the horizontal synchronizing signal section during the n-th horizontal scanning period,
FIG. 4 b ₂ ) shows the waveform of the horizontal synchronizing signal in the (n + 3) th horizontal scanning period.

The distortion generated during reproduction as described above improves the S / N, and the waveform of the horizontal synchronizing signal section becomes as shown in FIG. 5 due to the emphasis performed before performing FM modulation during recording. When the applied image signal is FM-modulated, overmodulation occurs in a portion corresponding to the front edge of the horizontal synchronizing signal, and the waveform distortion occurs during reproduction as described above.

Also, since the carrier signal used for FM modulation during recording is not normally synchronized with the horizontal synchronization signal of the image signal, the above-mentioned distortion occurs at the time of reproduction at different positions in each horizontal scanning period. Looks like

As described above, when the synchronizing signal is separated by the synchronizing signal separating circuit 13 in FIG. 2 from the reproduced image signal in which different distortions occur in each horizontal scanning period, for example, FIG. 4 b ₁ ), b the V ₁ shown in ₂₎ and Threading Shiyu hold level, when subjected to separation of the synchronization signal, the position of the front edge of the separated sync signal is deviated by a period represented by △ t in FIG.

In the still image signal storage device as shown in FIG. 3, the horizontal and vertical synchronizing signals or the horizontal and vertical synchronizing signals are synchronized with the edge of the synchronizing signal separated by the synchronizing signal separating circuit 13 in FIG. Sampling pulses are formed, and image data is written to the memory 31 in synchronization with the various signals formed. If the previous edge of the synchronization signal is shifted from its original position as described above, the image data memory The write timing to the memory 31 is shifted, and the image data read from the memory 31 in synchronization with the accurate synchronization signal is degraded in image quality due to the write timing shift generated when writing the data.

An object of the present invention is to solve the above-mentioned problems, and to provide an information signal processing device capable of suppressing deterioration of a synchronization signal.

[Means for solving the problem]

The information signal processing circuit of the present invention is a device that handles a video information signal having a synchronization signal including a vertical blanking period, receives the video information signal, and outputs the input video information signal except for the vertical blanking period. Correction means for outputting the signal of the period through a plurality of series-connected comb filters, and outputting the signal of the vertical blanking period without passing through the plurality of comb filters;
A synchronizing signal separating unit for separating a synchronizing signal from the information signal output from the correcting unit.

(Operation)

With the above-described configuration, a signal other than the vertical blanking period of the input video information signal passes through a plurality of additive comb filters, and the signal in the vertical blanking period passes through the plurality of additive comb filters. By outputting the synchronization signal without synchronization, a synchronization signal having a strong temporal correlation can be accurately separated.

〔Example〕

 Hereinafter, the present invention will be described using examples of the present invention.

FIG. 1 is a diagram showing a schematic configuration of a still image signal recording / reproducing apparatus to which the present invention is applied. In FIG. 1, the same components as those of the still image signal recording / reproducing device shown in FIG. 2 are denoted by the same reference numerals, and detailed description is omitted.

In FIG. 1, a reproduction signal reproduced by a magnetic head 7 is amplified by a reproduction amplifier 16 and then demodulated into an image signal by an FM demodulator 11, and a de-emphasis circuit 12 has a characteristic opposite to that of the emphasis at the time of recording. Image signal separation circuit 14, correction circuit 37
Supplied to

FIG. 6 shows a specific configuration of the correction circuit 37. In FIG. 6, the output of the de-emphasis circuit 12 shown in FIG. 1 inputted from an input terminal 37d is branched into two systems, one of which is supplied as it is to the H terminal of the switching switch 37c, and the other is delayed by one horizontal scanning period. circuit (1HDL) 37a ₁ ~37an an adder
N number of the addition-type comb filter which are respectively constituted by 37b ₁ ~37bn is supplied to a circuit that is configured are connected in series, after passing through the said circuit, is supplied to the L terminal of the changeover switch 37c .

FIG. 7 is an explanatory diagram of the effect of the correction circuit shown in FIG.

In the seventh, n to n + 7 indicate the scanning line numbers of the screen, a to d indicate the positions of the front edge of the horizontal synchronizing signal on the screen, respectively, and figure numbers a to c in FIG. This shows the state of the signals on the signal lines a to c.

FIG. 7A shows that the position of the horizontal synchronizing signal on the (n + 3) th line is suddenly shifted by .DELTA.t, and each time one of the addition type comb filters shown in FIG. b, c, d
Are disperse | distributed in the order of.

However, in order to prevent the above-described correction processing from being performed during the vertical blanking period, the switching switch 37c is set to the H side in the figure during the vertical blanking period, and is set to the L side during the other periods.
To the side.

The switching control of the switching switch 37c as described above is controlled by a control signal c output from the correction control circuit 39 shown in FIG.

The correction control circuit 39 is constituted by, for example, a monaural multivibrator, detects a PG pin provided on a core (not shown) of the magnetic sheet 8 by the PG coil 38, and outputs the PG pin periodically in a rotation cycle of the magnetic sheet 8. The PG detection pulse is inputted, and a control signal c which becomes H level for a predetermined period after the PG pulse is inputted is formed and supplied to the input terminal 37e of the correction circuit 37.

As described above, the reproduced image signal output from the de-emphasis circuit 12 is output as it is from the output terminal 37f to the synchronizing signal separating circuit 13 via the switching switch 37c during the vertical blanking period, and is added except during the vertical blanking period. The deviation of the time axis of the synchronization signal is dispersed by the comb filter and output to the synchronization signal separation circuit 13 by the output terminal 37f via the switching switch 37c, so that the synchronization signal separation circuit 13 separates each horizontal scanning period. This makes it possible to reduce the amount of time shift of the horizontal synchronizing signal.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide an information signal processing device capable of suppressing deterioration of a synchronization signal.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a still image signal recording / reproducing apparatus to which the present invention is applied. FIG. 2 is a schematic configuration diagram of a conventional still image signal recording / reproducing apparatus. FIG. 3 is a schematic configuration diagram of a conventional still image signal storage device. FIG. 4 is a waveform diagram of the reproduced image signal in FIG. FIG. 5 is a diagram showing a waveform change of the horizontal synchronizing signal by the emphasis processing in FIG. FIG. 6 is a diagram showing a configuration example of the correction circuit of FIG. FIG. 7 is an explanation of the effect of the correction circuit shown in FIG. 13: Synchronous signal separation circuit 37: Correction circuit 38: PG coil 39: Correction control circuit

Claims (1)

(57) [Claims] An apparatus for handling a video information signal having a synchronization signal including a vertical blanking period, wherein the video information signal is input, and a signal of the input video information signal in a period other than the vertical blanking period is Output by passing through a plurality of additive comb filters connected in series,
The vertical blanking period signal includes a correction unit that outputs the signal without passing through the plurality of additive comb filters, and a synchronization signal separation unit that separates a synchronization signal from an information signal output from the correction unit. An information signal processing circuit characterized by the following.