KR910009043Y1 - Phase auto-control circuit of synchronous signal - Google Patents

Abstract

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Description

Synchronization signal phase automatic conversion circuit

1 is a horizontal synchronization pulse waveform diagram of PAL and SECAM.

2 is a conventional synchronization signal conversion circuit.

3 is a horizontal synchronization signal phase automatic conversion circuit diagram according to the present invention.

4 is an operating waveform diagram of FIG.

* Explanation of symbols for the main parts of the drawings

10: composite video signal 20: horizontal synchronous pulse detection circuit

30: Integrating circuit 40: Synchronous state detection control circuit

50: synchronization signal conversion gating circuit 60: third buffer

70: image processing circuit

The present invention relates to a synchronous signal phase conversion circuit of a PAL and SECAM system combined television, and more particularly to a circuit for automatically converting the phase of the horizontal synchronization signal according to the PAL and SECAM system. Currently, TV broadcasting methods include PAL, SECAM, and NTSC.

The operation of signal processing for receiving television video signals, scanning them to a CRT (Cathode Ray Tube), and reproducing according to the broadcasting method is also different. With the development of television technology, a multi system for receiving a PAL, SECAM, NTSC composite video signal and reproducing a screen has emerged. However, as shown in FIGS. 1a and 1b of the phases of the horizontal synchronous pulses of the PAL method and the horizontal synchronous pulses of the SECAM method, horizontally applied to the horizontal drive stage regardless of the broadcasting method in the multi-system. The horizontal synchronization pulse phase conversion circuit is built in such that the phase of the synchronization pulse is always the same.

1A is a horizontal synchronization pulse of the PAL method, and FIG. 1B is a horizontal synchronization pulse of the SECAM method. The configuration of a conventional horizontal synchronous pulse phase conversion circuit embedded in the multi-system is as shown in FIG.

1 is a composite video signal, 2 is a horizontal synchronous pulse detection circuit, 3 is an inverting circuit which inverts the phase of an input signal, and 4 is a horizontal synchronous pulse according to a predetermined switching control signal. An analog switch 5 which selects and outputs the output of the detection circuit 2 and the inversion circuit 3, and 7 is a selection switch.

In the configuration of FIG. 1, the selection switch 7 is a manual switch switched by a user's selection. In the case of the PAL method, the selection switch 7 should be open. The analog switch 5 is switched by the selection use switch 7 so that the COM is connected to the terminal NC (normal close) when the selection switch 7 is open. In the case where the selector switch 7 is "on", the terminal COM should be connected to a terminal (normally open) connection ("on").

When the composite video signal 1 is input as a PAL composite video signal while the selection switch 7 is now switched off, the horizontal synchronous pulse detection circuit 2 performs the composite video signal 1. The synchronous separation is performed to detect only the horizontal sync pulses of the PAL method as shown in FIG. 1a and output them to the terminal NO of the inverting circuit 3 and the analog switch 4. At this time, since the control terminal of the analog switch 4 is open (hi-impdance), the terminal COM of the analog switch 4 is switched to the inverting circuit 3 through the terminal NC. . The horizontal synchronous pulse whose phase is inverted in the inversion circuit 3 is output to the terminal 6 connected to the horizontal drive terminal (not shown) through the terminals NC and COM of the analog switch 4. do.

Accordingly, it can be seen that the horizontal synchronization pulse of the PAL method as shown in FIG. 1a is outputted by being phase-inverted in phase with the horizontal synchronization pulse of the SECAM method. The horizontal drive stage for inputting the horizontal synchronous pulse from the terminal 6 applies the input horizontal synchronous pulse to a flyback transformer (FBT). If the composite video signal 1 of FIG. 2 is a SECAM composite video signal, the output from the horizontal synchronous pulse detection circuit 2 is separated and output as the signal of FIG. At this time, if the selection switch 7 is maintained in the open state (off), as described above, the output of the inverting circuit 3 is selected and outputted to the terminal 6 so that the horizontal of the SECAM method as shown in FIG. The synchronization signal is inverted and output.

Therefore, when the composite video signal 1 is a SECAM video signal, the selector switch 7 is switched "on" so that the terminal COM of the analog switch 4 is connected to the terminal NO. The output of the horizontal synchronous pulse detection circuit 2 must be output as it is to be output to the connection terminal 6 of the horizontal drive input terminal. Therefore, the user should appropriately select and switch the selector switch 7 according to the PAL and SECAM broadcasting methods. If the PAL system does not invert the horizontal sync pulse, it causes the TV screen to collapse (synchronizes) depending on the reception signal system. However, the synchronous signal phase conversion circuit as described above has been inconvenient as the user manually controls the selector switch 7 according to the reception television system to provide the synchronous pulse of the in-phase to the horizontal drive stage.

Accordingly, an object of the present invention is to detect horizontal sync pulses separately from a composite video signal according to a broadcast method, to detect a horizontal sync pulse state, and to automatically convert the separated horizontal sync pulses according to the detected state. Therefore, the present invention provides a synchronization signal phase automatic conversion circuit that always outputs a horizontal synchronization pulse in phase. Another object of the present invention is to provide a circuit for converting horizontal detection pulses, which are separated and outputted from a composite video signal, to a predetermined level and detecting a horizontal synchronization state as a result. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram according to the present invention, and outputs the horizontal synchronous pulse detection circuit 20 and the horizontal synchronous pulse detection circuit 20 for detecting and outputting only horizontal synchronous pulses from the input composite image signal 10. The coupling capacitor C1 for coupling the circuit to the subsequent stage, the integrating circuit 30 for integrating the horizontal synchronizing pulse through the capacitor C1 and converting it into a voltage of a predetermined level, and the resistors R1 and R2. The reference voltage generator 42 generating the reference voltage Vref by the resistance voltage divider ratio of the reference voltage and the reference voltage Vref of the reference voltage generator 42 and the output of the integrating circuit 30 are synchronized. A comparator CP1 for outputting a state detection signal, resistors R3, R4 and capacitor C2 for setting a synchronous state detection signal from the comparator CP1 to a control voltage of a predetermined level, and the control A first state buffer I1 that inverts the voltage to detect the synchronous state detection control signal CPCS. ) Is input to the synchronous state detection control circuit 40 and the output of the capacitor C1 to one terminal a, and the output of the first buffer I1 to the other terminal b. According to the input of the first terminal (AN1) and the output of the first gate (AN1) and the output of the second inverter (I2) for inverting the output of the capacitor (C1) to one side terminal (a) gating output a) and input the output of the comparator CP1 to the other terminal b so that the second and gate AN2 and the first and second AND gates AN1 are output according to the output of the comparator CP1. ), A synchronous signal conversion gating circuit 50 composed of first and second buffers BF1 and BF2 for amplifying and buffering the output of AN2, and the first and second buffers BF1, ( A third buffer 60 that amplifies the output of BF2 to a horizontal drive (not shown), and transmits the composite video signal 10 to the synchronization state detection signal CPCS. And an image processing circuit 7eO to process and output accordingly.

The integrating circuit 30 which integrates the horizontal synchronous detection pulses input in the configuration of FIG. 3 and outputs the DC voltage of a predetermined level, and synchronizes the output of the integrating circuit 30 with the internal reference voltage Vref. The synchronous state detection control circuit 40 for outputting the synchronous state detection signal according to the signal state is the synchronous state detection control signal generating means 45, and the synchronous signal conversion gating circuit 50 is the synchronous signal conversion gating means.

FIG. 4 is a waveform diagram for explaining the operation of FIG. 3, where FIG. 4a is a composite video signal of SECAM method, FIG. 4b is a horizontal synchronization pulse detection waveform diagram of FIG. 4a, and FIG. 4c is a horizontal pass-through filtering of FIG. 4b. Level waveform diagram at time and level waveform diagram of reference voltage Vref by resistances R1 and R2, FIG. 4d is a composite video signal diagram of PAL method, 4e is a horizontal synchronous pulse detection waveform diagram of 4d diagram, FIG. 4f is a level waveform diagram of the level waveform and the reference voltage Vref when the horizontal synchronization pulse of FIG. 4e is low-pass filtered. As shown in FIG. 4A and FIG. 4D, the positions of the composite video signal of the SECAM PAL method are opposite to each other. Hereinafter, the operation of FIG. 3 of the present invention will be described with reference to the waveform diagram of FIG.

When the composite video signal 10 input to the circuit configured as shown in FIG. 3 is a SECAM video signal as shown in FIG. 4A, the horizontal synchronous pulse detection circuit 20 performs synchronization separation from the composite video signal of FIG. It outputs SECAM type horizontal synchronous pulse like 4b. The output of the horizontal synchronous pulse detection circuit 20 is input to the integrating circuit 30 and one terminal a of the first and gate AN1 through the capacitor C1 and inverted by the second inverter I2. And input to one side terminal a of the second and gate AN2, respectively.

The integrating circuit 30 for inputting the synchronous pulse signal output from the horizontal synchronous pulse detection circuit 20 integrates the horizontal synchronous pulse of the SECAM method as shown in FIG. 4b and converts it into a DC voltage of a predetermined level. Input to the non-inverting terminal (+) of CP1). At this time, since the SECAM type horizontal synchronous pulse of FIG. 4B has a small average voltage, the DC level output from the integrating circuit 30 outputs a voltage V1 of a predetermined first level as shown in FIG. 4C.

On the other hand, the inverting terminal (-) of the comparator CP1, which inputs the suppressor V1 of the first level output from the integrating circuit 30 to the non-inverting terminal (+), is connected between the power supply voltage (B ⁺ ) and ground. A reference voltage based on the divided voltages of the connected resistors R1 and R2 is input. When this reference voltage is referred to as Vref, it becomes a voltage as shown in the following formula (1).

The reference voltage Vref set by Equation (1) will be mentioned later in the description of operation, but should be set larger than the first level voltage V1 of FIG. 4C.

Therefore, when the composite video signal 10 is the SECAM method as shown in FIG. 4a, the reference voltage Vref by the resistors R1 and R2 is the voltage V1 of the first level at which the output of the integrator 30 is output. The synchronization state detection signal CPCS, which is larger and is output from the comparator CP1, is a logic " low ". At this time, the output of the first inverter I1 that inverts the output of the comparator CP1 becomes “high”, so that logics are provided at the other terminals b of the first, second and gate AN1, and AN2. "High" and "low" are input respectively. SECAM type horizontal as shown in FIG. 4B, in which only the first AND gate AN1 is enabled due to the "low" output of the comparator CP1 and is input to one terminal a through the capacitor C1. The sync pulse is output as it is without phase shifting.

The signal gated from the first and gate AN1 is amplified by the first buffer BF1 and input to the third buffer 60. The third buffer 60 buffers the input synchronization signal to a horizontal drive (not shown) input connection terminal 65. The horizontal drive serves to apply an input horizontal synchronizing pulse to the FBT as is known. On the other hand, the synchronization state detection signal CPCS output from the comparator CP1 in a low state is input to the image processing circuit unit 70. At this time, the image processing circuit unit 70 for inputting the composite image signal 10 and the synchronization state detection signal CPCS in the "low" state output from the comparator CP1 is SECAM by the synchronization state detection signal CPCS. Image processing is performed in a manner to output the signal to the terminal 75.

Therefore, when the input composite video signal 10 is a SECAM video signal as shown in FIG. . If the composite video signal 10 input to the circuit of FIG. 3 is a PAL composite video signal, this is shown in FIG. 4D. That is, the PAL composite video signal of FIG. 4d is the same as that of the SECAM composite video signal of FIG. 4a. At this time, the horizontal synchronous detection circuit 20 detects and outputs only the horizontal synchronous pulse signal as shown in FIG.

The horizontal synchronous pulse output of FIG. 4E output from the horizontal synchronous pulse detection circuit 20 is transferred to each part through the capacitor C1 as described above. The integrating circuit 30 inputs the synchronously detected horizontal synchronizing pulse signal as shown in FIG. 4e, and integrates the horizontal synchronizing pulse signal of the PAL method to compare the voltage having the second level V2 as in FIG. 4f with comparator CP1. Input to the non-inverting terminal of (+).

The reason why the output of the integrating circuit 30 becomes the second level voltage V2 as shown in Fig. 4f is because the average voltage of the horizontal synchronizing pulse of Fig. 4e is large. At this time, the reference suppressor Vref according to formula (1) is input to the inverting terminal (-) of the comparator CP1, so that the comparator CP1 receives the second level voltage V2 and the reference voltage Vref of FIG. 4f. Will be compared and output. The reference voltage Vref set by Equation (1) must be less than the second level voltage V2 of FIG. 4f. Therefore, the reference voltage Vref should be set higher than the first level voltage V1 when the horizontal sync pulse of the SECAM method is integrated and less than the second level voltage V2 when the horizontal sync pulse of the PAL method is integrated. . Therefore, when the PAL composite video signal 10 is input, the sync state detection signal CPCS output from the comparator CP1 is output as logic "high", and the logic "high" is the power supply voltage B. ⁺ ) Level.

The output " high " of the comparator CP1 becomes a proper TTL level by the voltage dividing operation by the resistors R3 and R4, and is output to the image processing circuit unit 70 as a " high " state signal. It is input to the other terminal b of AN2). At this time, the "low" signal is input to the other terminal b of the first AND gate AN1 by the first inverter I1 which inverts the output of the comparator CP1 and is thus disabled. ) Cut off the input signal. The second and gate AN2 is enabled by the output " high " of the comparator CP1, and thus outputs a horizontal sync pulse of the PAL method inverted by the second inverter I2.

Accordingly, the 4e signal is inverted and input to the second buffer BF2, and the second buffer BF2 amplifies the predetermined signal and inputs the signal to the third buffer 60 as a signal having a predetermined amplitude. Therefore, the horizontal synchronization pulse input to the third buffer 60 may be a horizontal synchronization pulse of the PAL method having the same phase as the SECAM method. On the other hand, the image processing unit 70 for inputting the "high" state sync state detection signal CPCS output from the comparator CP1 and the composite video signal 10 of the PAL method performs image processing by the PAL method. And output to the terminal 75.

Therefore, the horizontal synchronization signal phase is automatically converted according to the phase state detection of the horizontal synchronization signal according to the broadcasting method, so that the horizontal synchronization signal of the same phase can be always input to the horizontal drive. As described above, the present invention provides a function of a multi-system for receiving and processing complex video signals of various broadcasting methods by automatically converting horizontal sync pulses having different phases according to the broadcasting method to the same phase and providing them to the horizontal drive stage for horizontal processing. There is an advantage to improve.

Claims (3)

A synchronization signal phase automatic conversion circuit of a multi-system which receives first and second broadcast video signals having opposite phases of horizontal sync pulses and performs image processing, wherein only horizontal sync pulses are separated and detected from an input video signal. A horizontal synchronous pulse detection circuit 20 to output and a gating control terminal connected to the horizontal synchronous pulse detection circuit 20, the first broadcast according to a logic state of a gating control signal input to the gating control terminal A synchronous signal conversion gating means 50 for passing the horizontal synchronous pulse of the method, inverting the horizontal synchronous pulse of the second broadcast method, and converting and outputting the converted synchronous pulse to the in-phase, and the horizontal synchronous pulse detection circuit 20. Detect the average voltage of the horizontal synchronization pulses which are separated and detected, and input the gating control signal according to the detected average voltage to the synchronization signal. Ring gating means 50, synchronous signal phase automatic conversion circuit characterized in that it consists of a synchronous state detection control signal generating means (45) for supplying to the control terminal of the gating. The synchronous state detection control signal generating means 45 integrates the horizontal synchronous pulses detected and output from the horizontal synchronous pulse detection circuit 20 and integrates them into a DC level, and divides a predetermined power supply voltage into a predetermined voltage. Comparing the reference voltage generating means 42 for generating the reference voltage of the level with the reference voltage of the reference voltage generating means 42 and the DC level from the integrating circuit 30, The synchronization signal is detected by detecting a horizontal synchronization state signal and a logic signal of a first level when the horizontal synchronization pulse of the first broadcast method is used, and a logic signal of a second level that is different from the logic signal of the first level when the second broadcast method is used. And a comparator (CP1) provided as a gating control signal of the conversion gating means (50). 3. The synchronizing signal conversion gating means 50 inputs a horizontal synchronizing pulse output from the horizontal synchronizing pulse detection circuit 10 to one terminal a and outputs an inverted output of the comparator CP1. A first end gate (AN1) input to the other terminal (B) and outputting a horizontal synchronous pulse input to the one terminal (a) according to the input of the other terminal (b), and the horizontal synchronous pulse detection circuit Input of the output of the second inverter (I2) inverting the output of the (20) to one terminal (a), input the output of the comparator (CP1) to the other terminal (b) to the output of the comparator (OP1) By amplifying and buffering the output of the second and gate (AN2) and the output of the first and second and gate (AN1), (AN2) and the second and gate (AN2) inverted by the second inverter (I2) by A synchronization signal phase automatic conversion circuit comprising first and second buffers (BF1) and (BF2).