JP2000092373A - Camera system and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a camera system and its control method where a configuration of a count decoder is simplified. SOLUTION: In the camera system where a phase of an external synchronizing signal is adjusted in compliance with a television system given externally and an internal synchronizing signal is generated based on the external synchronizing signal after its phase is adjusted, a field discrimination circuit 44 discriminates whether a field at the reception of the external synchronizing signal is an odd numbered field or an even numbered field, a vertical counter 41 is reset only when the discrimination results indicates either of the fields, and a reset value in the unit set to one field by a reset value setting section 46 is loaded to a vertical counter 41 via a gate circuit 45.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a camera system and a control method thereof, and more particularly to an externally synchronized camera system that operates the system based on a synchronization signal conforming to an externally supplied television system and a control method thereof. .

[0002]

2. Description of the Related Art In a surveillance camera system, a slave camera is usually synchronized by using a synchronization signal (a horizontal synchronization signal, a vertical synchronization signal, and a composite synchronization signal including these signals) of a master camera. This is a well-known technique called external synchronization. In this external synchronization, a process of matching the phase of the synchronization signal of the slave camera with the synchronization signal of the master camera is performed. At this time, video signals are ultimately input from a plurality of cameras to one monitor.

However, there is a time difference in the synchronization signal of the master camera reaching each slave camera due to a difference in the amount of delay of the transmission line depending on the installation location of the slave camera. Will be generated. for that reason,
In each slave camera, a phase shift is performed on a synchronization signal provided from the master camera so as to absorb a synchronization deviation generated on the monitor, thereby eliminating the synchronization deviation on the monitor.

[0004] A synchronization signal such as a horizontal synchronization signal and a vertical synchronization signal used on the slave side is generated based on the synchronization signal having undergone the phase adjustment. In particular,
Phase adjustment is performed on a horizontal synchronization signal supplied from the outside, and the internal horizontal synchronization signal generated on the slave side is phase-synchronized with the external horizontal synchronization signal after the phase adjustment, while 1H (H is the horizontal scanning period). ) A vertical counter that counts every cycle is reset by a vertical synchronization signal supplied from the outside, and a vertical synchronization signal on the slave side is generated based on a count value from a load value (reset value) at the time of resetting. ing.

[0005]

By the way, in the television system in which interlaced scanning is performed, one screen (one frame) is composed of an odd (ODD) field / even (EVEN) field.
The format of the synchronization signal is different between the odd field and the even field as shown in FIG. As described above, when the format of the synchronization signal is different for each field, when generating the vertical synchronization signal on the slave side, if the reset value loaded at the time of resetting the vertical counter is different between the odd field and the even field. Need to be done.

Further, when the phases of the external horizontal synchronizing signal and the internal horizontal synchronizing signal after the phase adjustment are the same, the reset value to be loaded into the vertical counter at the time of reset may be a fixed value for both odd and even fields. However, different reset values need to be loaded when the phase of the internal horizontal synchronization signal is advanced or delayed with respect to the external horizontal synchronization signal after the phase adjustment. Therefore, it is necessary to set three reset values for each field, that is, a total of six reset values.

There are a system using a horizontal synchronization signal and a vertical synchronization signal as an external synchronization signal given from the master camera, and a system using a composite synchronization signal including the horizontal synchronization signal and the vertical synchronization signal. In the case of the former method, the reset operation of the vertical counter is performed using the externally applied vertical synchronization signal as it is, whereas in the case of the latter method, the vertical synchronization signal is separated from the composite synchronization signal. Then, the reset operation of the vertical counter is performed using the vertical synchronization signal separated from the synchronization.

At this time, there is a timing difference between the vertical synchronizing signal directly taken in from the outside and the vertical synchronizing signal internally separated from the composite synchronizing signal. Therefore, also in this case, the reset value to be loaded into the vertical counter at the time of resetting needs to be different for each system.

In order to construct a camera system that can support both of these methods, a vertical counter is loaded with a different reset value for each method, and a different reset value is loaded for each method in an odd field and an even field. In addition, since it is necessary to load different reset values for in-phase, lagging, and leading phases for each field, a total of 12
Different reset values must be set,
The configuration of the count decoder for setting the reset value becomes very complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a camera system and a control method for the same, which can simplify the configuration of a count decoder.

[0011]

A camera system control method according to the present invention adjusts the phase of an external synchronization signal conforming to a television system supplied from the outside and adjusts the external synchronization signal after the phase adjustment. In a camera system that generates an internal synchronization signal based on an internal synchronization signal, it is determined whether the field at the time of input of the external synchronization signal is an odd field or an even field, and only when the determination result is one of the fields. A reset operation at the time of generation is performed.

A camera system according to the present invention is a camera system for realizing the above control method, comprising: a phase adjusting means for adjusting a phase of an external synchronizing signal; and an external synchronizing means having a phase adjusted by the phase adjusting means. A synchronizing signal generating means for generating an internal synchronizing signal based on the signal; a field discriminating means for discriminating whether a field at the time of inputting the external synchronizing signal is an odd field or an even field; Only when one of the fields is determined, the synchronous signal generating means is provided with a load means for loading a single reset value upon resetting.

In the camera system having the above configuration, the phase adjustment circuit adjusts the phase of the internal synchronization signal by:
The phase adjustment for the external synchronization signal is performed. The internal synchronization signal is generated by the synchronization signal generation means based on the externally adjusted external synchronization signal, so that the phase of the internal synchronization signal matches the phase of the external synchronization signal. Here, when generating the internal synchronization signal, field determination is performed when an external synchronization signal is input. Then, only when one of the odd field and the even field is determined, the reset operation is performed on the synchronization signal generation means, and a single reset value is loaded at the time of the reset.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing an example of the configuration of a camera system to which the present invention is applied. Here, a case where the signal processing system of the camera is realized by analog is described as an example, but it is needless to say that the present invention can be similarly applied to a case where the signal processing system is realized by digital. The camera system is used, for example, as a slave camera in a surveillance camera system.

In FIG. 1, an output signal (CCD signal) of a CCD image pickup device 11 is input to a signal processing circuit 12. The signal processing circuit 12 includes a circuit (S / H circuit) that samples and holds an output signal of the CCD image sensor 11;
The circuit has a circuit (AGC circuit) for amplifying the sample and hold output to a certain level and a circuit for converting a CCD signal into a video signal. The timing control circuit 13 is provided for generating a CCD drive signal for driving the CCD image sensor 11, a signal processing drive signal for driving the signal processing circuit 12, and the like.

FIG. 2 shows a specific circuit configuration of the timing control circuit 13 according to one embodiment of the present invention.
The timing control circuit 1 according to the present embodiment
Reference numeral 3 denotes both a system using a horizontal synchronization signal and a vertical synchronization signal as an external synchronization signal conforming to a television signal given from a master camera, and a system using a composite synchronization signal including a horizontal synchronization signal and a vertical synchronization signal. The circuit configuration is compatible.

In FIG. 2, the timing control circuit 13 has two synchronization signal input terminals 21, 22, a clock input terminal 23, three synchronization signal output terminals 24, 25,
26 and a phase control terminal 27.

In the timing control circuit 13, an input terminal of a sync separation circuit 28 is connected to one sync signal input terminal 21. This sync separation circuit 28
Is a composite synchronization signal MST-SYNC from the master camera.
Is input via the synchronization signal input terminal 21, the horizontal synchronization signal H included in the composite synchronization signal MST-SYNC is output.
D and the vertical synchronization signal VD. Since the horizontal synchronization signal HD and the vertical synchronization signal VD separated from the synchronization are signals based on the composite synchronization signal SYNC given from the outside, the external horizontal synchronization signal EXT-HD and the external vertical synchronization signal EXT-VD are hereinafter referred to. Shall be called.

In the sync separation circuit 28, an output terminal on the side from which the external horizontal sync signal EXT-HD is output is connected to one fixed contact a of the changeover switch 29, and the external vertical sync signal EX is output.
The output terminal on the side from which T-VD is output is a switch 30
Are connected to one of the fixed contacts a. The movable contact c of the changeover switch 29 is connected to the synchronization signal output terminal 24.

The other fixed contact b of the changeover switch 30 and the one fixed contact a of the changeover switch 31 are connected to the other synchronizing signal input terminal 22. The other fixed contact b of the changeover switch 31 is connected to one of the synchronization signal input terminals 21. The movable contact c of the changeover switch 30 is connected to the movable contact c of the changeover switch 32.

One fixed contact a of the changeover switch 32
Is connected to one fixed contact a of the changeover switch 33. The movable contact c of the changeover switch 31 is connected to the other fixed contact b of the changeover switch 33. The movable contact c of the changeover switch 33 is connected to the phase comparator (PC) 3
4 is connected to one input terminal. This phase comparator 3
4 is connected to the phase control terminal 27.

As a result, the comparison result of the phase comparator 34 is output from the phase control terminal 27 to the outside of the circuit, and is supplied as a control voltage to a VCO (voltage controlled oscillator) 36 via an LPF (low pass filter) 35. VCO36
Is the original oscillation clock 2 having a frequency twice as high as the 14 MHz master clock MCK, which is the reference clock of this system.
It oscillates with MCK, and the oscillation frequency changes according to the control voltage. The original oscillation clock 2MCK is taken into the timing control circuit 13 from the clock input terminal 23.

The captured original oscillation clock 2MCK
Is divided by で in a 分 frequency divider 37 to become a 14 MHz master clock MCK.
Given to. The internal HD generation circuit 38 is, for example, １ ／
A horizontal frequency signal fH having a cycle of 1H (H is a horizontal scanning period) is generated by a combination of a 55 frequency divider 39 and a 1/2 frequency divider 40, and is generated by a vertical counter 41 and a decoder 4.
2. It is applied to the other fixed contact b of the changeover switch 29 and the changeover switch 43, respectively.

The vertical counter 41 outputs the horizontal frequency signal fH
Is divided by 1/525 to obtain the vertical frequency signal fV.
Generated by the decoder 42 and the changeover switch 4
3 as one of the fixed contacts a, and as a slave vertical synchronization signal SLV-SYNC, a synchronization signal output terminal 25.
Output to outside the circuit. The reset terminal of the vertical counter 41 is connected to the other fixed contact b of the changeover switch 32.
It is connected to the. The decoder 42 outputs the horizontal frequency signal f
H, and generates a slave composite synchronization signal SLV-SYNC based on the vertical frequency signal fV, and outputs a synchronization signal output terminal 2
6 to output outside the circuit. The movable contact c of the changeover switch 43 is connected to the other input terminal of the phase comparator 34.

In the timing control circuit 13, for example, an external horizontal synchronizing signal EXT-HD and an external vertical synchronizing signal
A field discriminating circuit 44 is provided for discriminating whether a field when a synchronization signal is externally supplied is an odd field or an even field based on -VD. The result of the discrimination by the field discriminating circuit 44 is given to a gate circuit 45 as load means.

The gate circuit 45 also receives a mode signal set by a mode setting unit (not shown) and inputs a reset value set for each mode by a reset value setting unit 46 to the field discrimination circuit 44. The data is loaded into the vertical counter 41 according to the determination result. Here, each mode in the present embodiment uses a mode using a horizontal synchronization signal HD and a vertical synchronization signal VD (hereinafter, referred to as an HDVD input mode) and a composite synchronization signal SYNC as synchronization signals given from a master camera. Mode (hereinafter, referred to as a SYNC input mode).

Mode signals indicating these two input modes are set in a mode setting section (not shown), and are applied to the gate circuit 4 as described above and to the changeover switches 29 to 31 respectively. These changeover switches 29 to 31 are connected to the movable contact b according to the mode signal.
However, when in the SYNC input mode, H
In the DVD input mode, the switch is switched to the fixed contact b side.

Next, the circuit operation for each input mode in the timing control circuit 13 having the above configuration will be described.

First, the circuit operation in the HDVD input mode will be described with reference to the signal flow diagram of FIG. This H
In the DVD input mode, the phase adjustment circuit 48 is provided at the input stage of the synchronization signal input terminal 21 in order to adjust the phase of the horizontal synchronization signal MST-HD given from the master camera.
Is provided.

The horizontal synchronizing signal SFT-HD phase-shifted by the phase adjusting circuit 48 is taken into the timing control circuit 13 from the synchronizing signal input terminal 21.
Here, since the movable contacts c of all the changeover switches 29 to 33 and 43 are on the fixed terminal b side, the horizontal synchronization signal S
The FT-HD becomes one input of the phase comparator 34 via the changeover switches 31 and 33. Further, the horizontal frequency signal fH generated by the internal HD generation circuit 38 based on the master clock MCK becomes the other input of the phase comparator 34 via the changeover switch 43.

The phase comparator 34 outputs the horizontal synchronizing signal SFT-
HD and the phase of the horizontal frequency signal fH are compared, and phase difference information corresponding to the phase difference is output. This phase difference information is output from the phase control terminal 27 to the outside of the circuit, smoothed by the LPF 35, and supplied to the VCO 36 as its control voltage. The VCO 36 controls the frequency of the original oscillation clock 2MCK according to the control voltage.

That is, the phase comparator 34, LPF 35,
A PLL circuit is configured by a circuit system that generates the horizontal frequency signal fH based on the VCO 36 and the original oscillation clock 2MCK and provides the horizontal frequency signal fH to the phase comparator 34. This PLL
An external synchronization operation is performed by the circuit, and the horizontal frequency signal f
H goes through the changeover switch 29 to the synchronization signal output terminal 2
4 slave horizontal synchronization signal SLV-HD
Is the horizontal synchronizing signal MST given from the master camera.
-Synchronization with HD.

On the other hand, the vertical synchronizing signal MST-VD given from the master camera is taken into the timing control circuit 13 from the synchronizing signal input terminal 22 and directly sent to the vertical counter 41 via the changeover switches 30 and 32 as a reset signal. As a result, the reset operation for the vertical counter 41 is performed.

Here, the reset operation of the vertical counter 41 in the HDVD input mode will be described with reference to FIGS.
This will be described with reference to the timing chart of FIG. FIG.
FIG. 5 shows a case of an odd field of a television signal of the EIA system (NTSC-compatible black and white system), and FIG. 5 shows a case of an even field. In these figures,
WND is a field discrimination pulse in this mode.
In addition, the numbers described in the horizontal synchronization signal SLV-HD are:
The count value of the vertical counter 41 is shown.

First, a reset operation in the case of an odd field will be described with reference to the timing chart of FIG. In FIG. 4, (1) indicates that the phase adjustment amount is 0,
That is, when the horizontal synchronizing signal MST-HD and the horizontal synchronizing signal SFT-HD after the phase shift are in phase, (2) indicates that the horizontal synchronizing signal SFT-HD is in phase with the horizontal synchronizing signal MST-HD up to 〜H. (3) indicates that the horizontal synchronizing signal MFT-HD is delayed with respect to the horizontal synchronizing signal SFT.
−HD has advanced in the range of ３H to 1H, respectively.

In FIG. 4, the timing at which the vertical counter 41 is reset is determined by the vertical synchronizing signal MST-V.
This is the falling timing of D. The vertical counter 41 is reset at the falling timing, and a reset value is loaded into the vertical counter 41 during this reset operation. The count-up timing of the vertical counter 41 is a timing immediately before the horizontal synchronization signal SLV-HD falls.

In the reset operation of the vertical counter 41 in the odd field, as is clear from the timing chart of FIG. 4, the reset value "0" is set at the time of in-phase (1) and at the time of phase advance (3), and at the time of phase delay. In (2), it is necessary to load the reset value “524” into the vertical counter 41, respectively.

Next, a reset operation in the case of an even field will be described with reference to the timing chart of FIG. In FIG. 5, (1) indicates the horizontal synchronization signal MS.
When the T-HD and the horizontal synchronization signal SFT-HD have a phase relationship of 1 / 2H, (2) shows the horizontal synchronization signal MST-HD.
The horizontal synchronization signal SFT-HD is ＨH to 〜.
When the phase is delayed in the range up to H, (3) indicates that the horizontal synchronizing signal SFT-HD is 1 /
The case where the phase is advanced in the range of 4H to 1 / 2H is shown.

In the reset operation of the vertical counter 41 in this even field, as is apparent from the timing chart of FIG. 5, the reset operation is performed regardless of the phase (1), the phase (2), and the phase advance (3). The value (load value) is common to “262”.

Therefore, in this embodiment, the reset value setting unit 46 shown in FIG. 2 uses a single reset value "262" for the even field for the HDVD input mode.
Is set in advance. In the HDVD input mode, the horizontal synchronizing signal MST-HD and the vertical synchronizing signal M
Only when the field when the ST-VD is input is determined by the field determination circuit 44 to be an even field, the gate circuit 4 based on the determination result.
5 loads a single reset value “262” from the reset value setting unit 46 to the vertical counter 41.

As described above, when the HDVD input mode is set, the reset value of the vertical counter 41 is set to "26" at the time of the reset operation of the vertical counter 41 only in the even field based on the field determination result.
By loading "2", normal operation can be performed irrespective of the phase of the slave-side synchronization signal with respect to the master-side synchronization signal.
During the reset operation, there is no need to determine the phase relationship of the horizontal synchronizing signal SFT-HD with respect to the horizontal synchronizing signal MST-HD, that is, to determine in-phase / slow-phase / advance-phase. Can greatly reduce the circuit scale.

Further, it is not necessary to preset a reset value corresponding to each of the in-phase / late-phase / lead-phase relations for each of the odd field / even field.
For the HDVD input mode, only a single reset value, that is, a reset value “262” needs to be set.
There is no need to use a decoder having a complicated circuit configuration as the reset value setting unit 46 corresponding to a count decoder for presetting a reset value, and the reset value can be realized with an extremely simple circuit configuration.

Next, the circuit operation in the SYNC input mode will be described with reference to the signal flow diagram of FIG.

The composite synchronization signal MST-SYNC given from the master camera is taken into the timing control circuit 13 from the synchronization signal input terminal 21 and then given to the synchronization separation circuit 28. Then, in the sync separation circuit 28, the external horizontal sync signal EXT-HD and the external vertical sync signal EX are converted from the composite sync signal MST-SYNC.
T-VD is separated.

Here, the movable contacts c of the changeover switches 29 to 31 are on the fixed contact a side, and the changeover switches 32, 3
Since 3,43 movable contacts c are on the fixed contact b side,
The external horizontal synchronizing signal EXT-HD is output from the synchronizing signal output terminal 24 to the outside of the circuit via the changeover switch 29. At this time, since the phase adjustment circuit 49 is provided between the synchronization signal output terminal 24 and the synchronization signal input terminal 22, the external horizontal synchronization signal EXT-HD is phase-shifted (phase adjusted) by the phase adjustment circuit 49. Is done.

Then, the horizontal synchronizing signal SFT-HD after the phase shift is taken into the circuit from the synchronizing signal input terminal 22 and becomes one input of the phase comparator 34 via the changeover switches 31 and 33. Further, the horizontal frequency signal fH generated by the internal HD generation circuit 38 based on the master clock MCK becomes the other input of the phase comparator 34 via the changeover switch 43. Phase comparator 34
Compares the phase of the horizontal synchronization signal SFT-HD with the phase of the horizontal frequency signal fH, and supplies information corresponding to the phase difference to the VCO 36 via the phase control terminal 27 and the LPF 35 as the control voltage.

Under the control of the PLL loop, the external synchronization operation is performed in the same manner as in the case of the above-described HDVD input mode. On the other hand, the external vertical synchronization signal EXT-VD separated by the synchronization separation circuit 28 is supplied to the changeover switch 30,
The reset operation for the vertical counter 41 is performed by being directly supplied as a reset signal to the vertical counter 41 via 32.

Here, the reset operation of the vertical counter 41 in the SYNC input mode will be described with reference to FIGS.
This will be described with reference to the timing chart of FIG. FIG.
8 shows a case of an odd field of a television signal of the EIA system, and FIG. 8 shows a case of an even field. In these figures, the numbers described in the horizontal synchronization signal SLV-HD indicate the count values of the vertical counter 41.

First, a reset operation in the case of an odd field will be described with reference to the timing chart of FIG. In FIG. 7, (1) indicates that the phase adjustment amount is 0,
That is, when the external horizontal synchronizing signal EXT-HD and the phase-shifted horizontal synchronizing signal SFT-HD have the same phase, (2) indicates the horizontal synchronizing signal SFT with respect to the external horizontal synchronizing signal EXT-HD.
-When the HD is delayed in the range from the same phase to 1 / 2H,
(3) shows the case where the horizontal synchronizing signal SFT-HD is advanced in the range of 1 / 2H to 1H with respect to the external horizontal synchronizing signal EXT-HD.

In FIG. 7, the timing at which the vertical counter 41 is reset is determined by the external vertical synchronizing signal EXT.
-The falling timing of VD. The vertical counter 41 is reset at the falling timing, and a reset value is loaded into the vertical counter 41 during this reset operation. The count-up timing of the vertical counter 41 is a timing immediately before the horizontal synchronization signal SLV-HD falls.

In the resetting operation of the vertical counter 41 in the odd field, as is apparent from the timing chart of FIG. 7, the vertical counter 41 is reset regardless of the phase (1), the phase delay (2) and the phase advance (3). The reset value (load value) to be loaded into the counter 41 is common to “3”.

Next, a reset operation in the case of an even field will be described with reference to the timing chart of FIG. In FIG. 8, (1) shows the case where the external horizontal synchronizing signal EXT-HD and the horizontal synchronizing signal SFT-HD are in phase, and (2) shows the horizontal synchronizing signal SFT-HD with respect to the external horizontal synchronizing signal EXT-HD. (3) is the external horizontal synchronizing signal EXT-H
The horizontal synchronization signal SFT-HD for D is ＨH to 1H
In each case, the phase is advanced in the range up to.

In the reset operation of the vertical counter 41 in this even field, as is clear from the timing chart of FIG. 8, the reset value "266" is set at the time of in-phase (1) and at the time of phase advance (3), and For (2), it is necessary to load the reset value “265” into the vertical counter 41, respectively.

Therefore, in the present embodiment, a single reset value "3" is set in advance for the odd field in the reset value setting section 46 shown in FIG. 8 for the SYNC input mode. In the SYNC input mode, the gate circuit 45 is reset based on the determination result only when the field when the composite synchronization signal MST-SYNC is input is determined by the field determination circuit 44 to be an odd field. A single reset value “3” is loaded from the value setting unit 46 to the vertical counter 41.

As described above, when the SYNC input mode is set, the vertical counter 41 is reset and the reset value "3" is loaded only in the odd field based on the result of the field discrimination. Normal operation can be performed irrespective of the phase of the synchronization signal on the slave side with respect to this synchronization signal. Therefore,
At the time of reset operation of the vertical counter 41, the horizontal synchronizing signal M
Since there is no need to determine the phase relationship of the horizontal synchronization signal SFT-HD with respect to ST-HD, that is, it is not necessary to determine in-phase / slow-phase / fast-phase.
The determination circuit becomes unnecessary, and the circuit size can be significantly reduced by reducing the number of gates accompanying this.

Further, it is not necessary to preset a reset value corresponding to each of the in-phase / late-phase / lead-phase relationships for each of the odd field / even field.
For the SYNC input mode, it is only necessary to set a single reset value, that is, a reset value “3”. Therefore, a decoder having a complicated circuit configuration is used as the reset value setting unit 46 for setting the reset value in advance. There is no need to use it, and it can be realized with a very simple circuit configuration.

In the above embodiment, the case where the television system is applied to the EIA system has been described. However, this is merely an example, and the NTSC system, the PAL system, and the CCIR system which is a black and white system compatible with the PAL system. Basically, the present invention can be applied to any system that performs interlace scanning.

[0059]

As described above, the phase adjustment is performed on the external synchronization signal conforming to the television system supplied from the outside, and the internal synchronization signal is generated based on the external synchronization signal after the phase adjustment. In the camera system, it is determined whether the field at the time of input of the external synchronization signal is an odd field or an even field, and only when the determination result is one of the fields, the reset operation for generating the internal synchronization signal is performed. By doing so, it is not necessary to prepare a reset value for both fields to be loaded at the time of the reset operation, so that the configuration of the count decoder for setting the reset value can be greatly simplified.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating an example of a configuration of a camera system to which the present invention is applied.

FIG. 2 is a block diagram showing a specific circuit configuration of a timing control circuit according to one embodiment of the present invention.

FIG. 3 is a signal flow chart for explaining a circuit operation in an HDVD input mode.

FIG. 4 is a timing chart in the case of EIA / ODD in the HDVD input mode.

FIG. 5 shows EIA / EVEN in HDVD input mode.
6 is a timing chart in the case of FIG.

FIG. 6 is a signal flow diagram for describing a circuit operation in a SYNC input mode.

FIG. 7 is a timing chart in the case of EIA / ODD in the SYNC input mode.

FIG. 8 shows EIA / EVEN in the SYNC input mode.
6 is a timing chart in the case of FIG.

FIG. 9 is a waveform diagram showing a format of ODD / EVEN of a synchronization signal.

[Explanation of symbols]

11: CCD imaging device, 13: timing control circuit, 28: sync separation circuit, 34: phase comparator, 36 ...
VCO (Voltage Controlled Oscillator), 38 Internal HD generation circuit,
41: vertical counter, 44: field discriminating circuit, 45
... gate circuit, 46 ... reset value setting unit, 48, 49 ...
Phase adjustment circuit

Claims (4)

[Claims] 1. A camera system for performing phase adjustment on an external synchronization signal compliant with a television system given from outside and generating an internal synchronization signal based on the external synchronization signal after the phase adjustment. It is characterized in that it is determined whether the field at the time of input of the synchronization signal is an odd field or an even field, and the reset operation for generating the internal synchronization signal is performed only when the determination result is one field. Control method of camera system. 2. A camera system for operating a system based on an external synchronization signal based on an externally supplied television system, comprising: a phase adjustment unit configured to adjust a phase of the external synchronization signal; Synchronizing signal generating means for generating an internal synchronizing signal based on the external synchronizing signal phase-adjusted by the adjusting means; and field discriminating means for discriminating whether a field at the time of inputting the external synchronizing signal is an odd field or an even field. And loading means for loading the synchronization signal generating means with a single reset value at the time of resetting only when one of the fields is determined by the field determining means. Camera system. 3. The camera system according to claim 2, wherein said external synchronizing signal is a horizontal synchronizing signal and a vertical synchronizing signal, and said phase adjusting means adjusts a phase of said horizontal synchronizing signal. . 4. The external synchronizing signal is a composite synchronizing signal including a horizontal synchronizing signal and a vertical synchronizing signal, and the phase adjusting means adjusts a phase of the horizontal synchronizing signal synchronously separated from the composite synchronizing signal. 3. The camera system according to claim 2, wherein the operation is performed.