JPH08331441A - Television camera device - Google Patents

Abstract

PURPOSE: To provide a television camera device by which video signals in many kinds of systems can be generated and outputted with inexpensive configuration. CONSTITUTION: In CCD 12a, 12b and 12c, the number of horizontal picture elements is 960 being 1/2 times of horizontal picture elements in high-definition television standard. The write timing pulses of processors 23a, 23b and 23c are generated by a PLL circuit consisting of a phase comparator 16, a VCXO17 and a timing pulse generating circuit 18. The read timing pulses of processors 23a, 23b and 23c are generated by a PLL circuit consisting of a phase comparator 24, a VCXO25 and a timing puls generating circuit 26. The read digital signals of the processors 23a, 23b and 23c are subjected to a picture element shifting processing, converted into analog signals and outputted from synchronizing signal adding circuits 30a, 30b and 30c as the primary color signals of B, G and R.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television camera device, and more particularly to a television camera device for picking up an image of an object and generating and outputting a high definition video signal having a higher definition than a standard video signal.

[0002]

2. Description of the Related Art In recent years, the number of scanning lines of a video signal and the aspect ratio of a screen of a monitor device have been changed due to the fusion of television and computer from the idea of multimedia, widening of television and high image quality of computer display. It has become very large.

Therefore, conventionally, there has been known a television camera device which internally uses a system converter (scan converter) to perform system conversion such as aspect ratio conversion to generate and output a video signal of a desired system. Examples of this system conversion device include computer graphics images and CAD images produced by various computers whose aspect ratio is adjusted to 4: 3, for example, and converted into standard system video signals of NTSC system or PAL system, Converts HDTV (high-definition) images to the above standard system video signals, and automatically determines the scanning system regardless of whether the scanning system is an interlace system or a non-interlace system, and is a high-quality NTSC system or PAL system format. It has a function of converting into a video signal of, and further into various video signal outputs such as a composite video signal, a component video signal, three primary color signals, a luminance signal and a carrier color signal.

Further, a television camera device for generating and outputting a high-definition image signal having a higher definition than the standard-type image signal has been conventionally known, but this one uses an image pickup device dedicated to the high-definition system. Therefore, since the conversion of the number of scanning lines is unnecessary and the system conversion circuit is not provided, the cost can be lower than that of the conventional television camera device having the system conversion circuit.

[0005]

However, in the former television camera device among the above-mentioned conventional television camera devices, a video signal of a desired system including a high-definition system, which is internally provided, captures a video signal. There is a problem that the entire device is extremely expensive because the system conversion device that converts the system into 1) includes many functions such as a signal capturing circuit and other various circuits for enhancing versatility.

By the way, the high-definition standard is established not only for the number of scanning lines but also for the number of horizontal pixels and the sampling rate from the current situation of digital image processing and image pickup using a charge coupled device (CCD) image pickup device as is well known. The number of scanning lines is 1125 (the number of effective scanning lines is 1035).
Book), the aspect ratio of the screen is 9:16, and the number of effective horizontal pixels of the luminance signal and the three primary color signals is 1920, so the shape of the pixel is not square.

However, since it is advantageous to make the pixels square in contour (image edge enhancement) processing and the like, the number of effective scanning lines is set to make each pixel having 1920 effective horizontal pixels square. From 1035 to 1080 (= 192
There is also a proposal to make it 0x9 / 16) books.

However, the latter television camera device among the above-mentioned conventional television camera devices has a dedicated image pickup device and internal circuit which conform to the above-mentioned high-definition standard, and therefore has 1080 effective scanning lines. There is a problem that the method cannot be applied.

The present invention has been made in view of the above points,
An object of the present invention is to provide a television camera device capable of generating and outputting video signals of many types of systems with an inexpensive configuration.

[0010]

In order to achieve the above object, the present invention provides a digital signal of a video signal obtained by imaging with an image sensor having a horizontal pixel number smaller than the target effective horizontal pixel number. The AD conversion means for converting the image signal into an image signal, the first timing pulse generation means for generating and outputting the timing pulse synchronized with the external horizontal synchronizing signal, and the drive signal output from the first timing pulse generation means for driving the image sensor. Drive means and second timing pulse generation means for receiving the first timing pulse output from the first timing pulse generation means as an input signal and generating a second timing pulse synchronized with the first timing pulse. , The output digital signal of the AD conversion means is written based on the first timing pulse, and the written digital signal is changed to the second digital signal. The digital signal processing means for reading out based on the timing pulse and the digital signal read out from the digital signal processing means are converted into an analog signal based on the second timing pulse, and at the same time the target effective horizontal by the pixel shifting technique. An analog video signal output means for generating and outputting a video signal having the number of pixels and added with a composite sync signal is provided.

Here, the first timing pulse generating means includes a first phase comparator and a first variable frequency oscillator whose output oscillation frequency is variably controlled by an output phase error voltage of the first phase comparator. A timing generator that divides the output signal of the first variable frequency oscillator to generate a drive signal, and a first timing pulse generator that generates various first timing pulses based on the output signal of the timing generator. A first PLL circuit composed of
The timing pulse generating means of is a second phase comparator,
A second variable frequency oscillator whose output oscillation frequency is variably controlled by an output phase error voltage of the second phase comparator;
Of the variable frequency oscillator, and a second PLL circuit composed of a second timing pulse generation circuit for generating various second timing pulses and dividing the output signal of the variable frequency oscillator. It is characterized in that the horizontal synchronizing signal or the output signal of the second timing pulse generating circuit is input, and the first timing pulse or the external horizontal synchronizing signal is input to the second phase comparator.

Further, according to the present invention, when the target television standard is N effective scanning lines, effective horizontal pixel number M pixels (M is an even number), and the aspect ratio of the screen is a: b, the image sensor is , The number of effective scanning lines is (M × a / b), and the number of effective horizontal pixels is M / 2 pixels.

Further, according to the present invention, the frequency of the second timing pulse output from the second timing pulse generating means to the digital signal processing means as a read pulse is applied to the digital signal processing means as a write pulse. To the frequency of the timing pulse of {N / (M
Xa / b)} is set to a frequency that is a natural multiple of the horizontal scanning frequency that is closest to the multiplied value, and an effective horizontal pixel (N × b / a) pixel analog video signal is generated with N effective scanning lines. It is configured to output.

[0014]

According to the present invention, the output digital signal of the AD conversion means is written based on the first timing pulse, and the written digital signal is converted into the target number of effective horizontal pixels based on the second timing pulse. After the reading, the analog video signal output means converts the analog signal based on the second timing pulse and outputs the video signal with the composite sync signal added.
Since writing and reading can be done independently,
Generates and outputs a video signal with a desired number of effective scanning lines with a desired number of effective horizontal pixels such that each pixel has a square shape even if the number of effective horizontal pixels of the image signal intended by the image sensor is smaller. be able to.

In the present invention, the target television standard is defined by N effective scanning lines and M effective horizontal pixels (M pixels).
Is an even number), and when the aspect ratio of the screen is a: b, the number of effective scanning lines is (M × a / b) and the number of effective horizontal pixels is M / 2 pixels. It is possible to obtain a video signal in which the number of effective scanning lines is (M × a / b) with several M pixels and the shape of each pixel is square.

Further, according to the present invention, the horizontal scanning closest to the value obtained by multiplying the frequency of the second timing pulse by {N / (M × a / b)} times the frequency of the first timing pulse applied as the writing pulse. By setting the frequency to a natural multiple of the frequency, it is possible to generate and output the second timing pulse used as the read pulse by using the second PLL circuit, and the number of effective horizontal pixels is N when the number of effective scanning lines is N. It is possible to generate and output an analog video signal of (N × b / a) pixels in which each pixel has a square shape.

[0017]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a television camera device according to the present invention. The present embodiment is a television camera device that generates and outputs a video signal conforming to the high definition standard. Here, the high-definition standard defines that the number of scanning lines is 1125 (the number of effective scanning lines is 10 as described above).
35), the aspect ratio of the screen is 9:16, the number of effective horizontal pixels of the luminance signal and the three primary color signals is 1920, the number of effective horizontal pixels of the color difference signal is 960, the field frequency is 60 Hz, and the horizontal scanning frequency is 33.75 kHz. The pixel shape is not square.

In the present embodiment, in consideration of the fact that the square shape of each pixel is advantageous in contour processing and the like, a general-purpose CCD is used to generate and output a high-definition video signal in which each pixel shape is square. Is. Here, the number of effective horizontal pixels remains the same as the standard, and the number of effective horizontal pixels 1920
In order to make each of the pixels into a square, as shown in FIG. 2, the number of effective scanning lines is from 1035 to 1080 (= 192).
0x9 / 16) books are required. Further, in order to make each pixel having the number of effective horizontal pixels 1920 a square while keeping the number of effective scanning lines the same as the standard number of 1035, the number of effective horizontal pixels is from 1920 to 1840 (= 1035 × 1).
It is necessary to change to 6/9).

Therefore, the present embodiment is designed so as to be compatible with both of the above-described effective scanning line numbers, and the number of effective scanning lines is 1080 and the number of effective horizontal pixels is 1920 pixels or the number of effective scanning lines is 1035. And the number of effective horizontal pixels is 184
A high-definition video signal having 0 pixels is generated and output.

Further, according to the standard, the difference in the number of effective scanning lines becomes the difference in the vertical blanking period as it is, but the effective horizontal time is the same in both the above-mentioned system of 1080 effective scanning lines and the system of 1035. Therefore, in the method of 1035 effective scanning lines, the horizontal pixel read rate is set to (1840/192).
0), which is changed to C in the present invention.
The feature is that the process is not performed by the CD read clock, but performed in the subsequent process.

Next, the configuration and operation of the first embodiment shown in FIG. 1 will be described. In the figure, an image from a subject (not shown) is separated into three primary colors of blue (B), green (G) and red (R) by a prism 11 via a lens (not shown),
Each primary color signal is CCD 12a, 12b and 12c
Is incident on and forms an image.

Here, the CCD 12 used in this embodiment.
The pixels a, 12b, and 12c are not dedicated to the extremely expensive high-definition system in which the number of horizontal pixels is the same as the high-definition standard of 1920 pixels but are 960 pixels which are ½ times the number of horizontal pixels of the high-definition standard. An inexpensive CCD to which the shift processing technique is applied is used (for example, μpD3621). However, in this embodiment, the CCD
The images formed on 12a, 12b, and 12c are designed so that the number of effective scanning lines is 1080, the number of effective horizontal pixels is 1920 (960 for a CCD alone), and the aspect ratio of the screen is 9:16.

Here, the CCD 12a having 960 effective horizontal pixels and 1080 effective horizontal scanning lines used in this embodiment,
In 12b and 12c, when a circle is imaged with 1035 effective horizontal scanning lines, which is the same as in the high-definition system, the aspect ratio of the screen in this case is 8.625: 1 as shown in FIG.
6 is displayed as it is on a high-definition display having a screen aspect ratio of 9:16, it becomes a vertically elongated ellipse having a long axis in the vertical direction as shown in FIG. Therefore, by the signal processing in the apparatus of this embodiment, horizontal pixels are formed on both sides of the screen as shown in FIG.
A total of 0 pixels are cut off and 40 pixels are discarded, and the image is stretched in the horizontal direction to obtain a perfect circular image having a screen aspect ratio of 9:16.

Since each of the B, G, and R primary color signals of 960 horizontal pixels output from the CCDs 12a, 12b, and 12c includes signals other than video signal components, these primary color signals are sampled. And the hold circuits (S & H circuits) 13a, 13b, and 13c are separately supplied, and only the video signal components are sampled and held and output, and then supplied to the preprocessing circuits 14a, 14b, and 14c, respectively.

The preprocessing circuits 14a, 14b and 14c are respectively the next stage 8-bit AD converters (ADC) 15a, 1a.
In order to supplement the dynamic range of 5b and 15c, the input video signal components (primary color signals) are subjected to processing such as gamma processing, knee processing, matching of CCD output and ADC input level, and so on to ADCs 15a, 15b and 15c. And is converted into an 8-bit digital signal.

On the other hand, the phase comparator 16, the voltage controlled crystal oscillator (VCXO) 17, the timing pulse generation circuit 18
The first phase-locked loop (PLL) circuit including the timing generator 20 and the timing generator 20 generates clocks for the above circuits. VCXO17 is the basic 7
Self-oscillates at 4.25 MHz. The timing pulse generating circuit 18 is a circuit including a counter and a logic circuit, and generates a horizontal rate timing pulse and a vertical rate timing pulse.

For the external synchronization (GEN LOCK) function of the camera, an external composite synchronization signal is separated into a horizontal synchronization signal and a vertical synchronization signal (frame detection signal) by a synchronization separation circuit (not shown), and the horizontal synchronization signal is divided into horizontal synchronization signals. The signal is supplied to the phase comparator 16, where the timing pulse generation circuit 18
After being phase-compared with the timing pulse of the horizontal rate, converted into a phase error voltage according to those phase errors, it is supplied as a control voltage to the VCXO 17 to variably control its output oscillation frequency.

The output signal of the VCXO 17 is supplied to the timing pulse generation circuit 18. This phase comparator 1
6, the first PLL circuit including the VCXO 17, the timing generator 20, and the timing pulse generation circuit 18 operates so that the phase error in the phase comparator 16 becomes zero.
Regarding the vertical, the timing pulse generation circuit 18 and the synchronization signal generator (SSG) 19 are reset at the vertical timing so as to establish synchronization. Sync signal generator (S
SG) 19 is substantially integrated with the timing pulse generating circuit 18 to generate a horizontal synchronizing signal, a vertical synchronizing signal and a blanking signal.

The output signal of the VCXO 17 is also supplied to the timing generator 20. Timing generator 20
Is composed of a timing generator (TG) and first and second phase adjusters (neither is shown).
The output signal of O17 is supplied to the timing generation section (the synchronization pulse is also input from the timing pulse generation circuit 18 but omitted), and here, the drive signals necessary for driving the CCDs 12a, 12b and 12c are generated. , The drive signal is supplied to the drive circuit 21 to amplify the power, and then C
While supplying to the CDs 12a, 12b, and 12c, a sampling pulse is generated by the timing generator, and the sample and hold circuit 13a is passed through the first phase adjuster.
13b and 13c, respectively.

At the same time, the timing generator 2
The timing generator within 0 halves the output signal frequency from the VCXO 17 from 74.25 MHz to 37.125 MHz.
The frequency is divided, and the divided pulse is supplied to the timing pulse generation circuit 18 through the internal second phase adjuster. As a result, the phase comparator 16, the VCXO 17, the timing generator 20, and the timing pulse generation circuit 18 constitute a PLL circuit, and the CCD drive signal and the output timing pulse of the timing pulse generation circuit 18 which are synchronized with the external input horizontal synchronization signal. And manage them constantly. Further, the pulse generated by the timing generation unit in the timing generator 20 can be adjusted in phase by the internal second phase adjuster, so that the ADCs 15a, 1
Fine adjustment of the fetch timing of 5b and 15c is performed.

On the other hand, a black level clamp pulse is sent from the timing pulse generation circuit 18 to the preprocessing circuits 14a, 14b and 14c, and the ADCs 15a, 15b and 15c.
The strobe signal is supplied to each. Processor 2
In 3a, 23b and 23c, the digital primary color signals from the ADCs 15a, 15b and 15c are input to the data input terminals, the write pulse from the timing pulse generation circuit 18 is input to the terminal SWCK, and the signal for controlling the write start timing is write enable. The master clock is input to the terminal WE and further to the terminal MCK. The operation of the processors 23a, 23b and 23c will be described later.

Further, the output pulse of the timing pulse generating circuit 18 is supplied to the phase comparator 24, where it is phase-compared with the pulse from the timing pulse generating circuit 26,
After setting the phase error voltage according to the phase difference between them, VC
It is supplied to the XO 25 to variably control its output oscillation frequency. The output signal of the VCXO 25 is supplied to the timing pulse generation circuit 26. This phase comparator 24, VCXO2
5 and timing pulse generating circuit 26
Timing pulses are generated by the LL circuit.

Here, the output oscillation frequency of the VCXO 25 is a value obtained by dividing the product of the output oscillation frequency of the VCXO 17 on the writing side and the number of effective scanning lines of the television system by the number of effective scanning lines of the CCD 71.562 MHz (= 74. 25 MHz
X 1035/1080), but the PLL must be an integer multiple of the horizontal scanning frequency of 33.75 kHz.
Since the circuit cannot be configured, the above-mentioned 71.5 is used in this embodiment.
It is set to a frequency that is an integral multiple of the horizontal scanning frequency closest to 62 MHz.

That is, the output oscillation frequency of the VCXO 17 of 74.25 MHz is 2200 times the horizontal scanning frequency of 33.75 kHz, which is 1035/1080.
When multiplied, it becomes 2108.333 times the horizontal scanning frequency, so the output oscillation frequency of the VCXO 25 is set to 71.145 MHz which is 2108 times the horizontal scanning frequency.

The timing pulse generation circuit 26 is a circuit composed of a counter and a logic circuit and produces a horizontal rate timing pulse and a vertical rate timing pulse. The phase comparator 24 controls the relationship between the timing pulse generated by the timing pulse generation circuit 26 and the timing pulse generated by the timing pulse generation circuit 18, and is generated by the timing pulse generation circuit 18. The horizontal rate timing pulse and the horizontal rate timing pulse generated by the timing pulse generating circuit 26 are compared in phase to output an error voltage, and V
By variably controlling the oscillation frequency of the CXO 25, it operates so as to make the phase error zero. As a result, the write-side timing and the read-side timing of the processors 23a, 23b, and 23c are managed.

Here, in the present embodiment, processing for doubling the number of horizontal pixels is performed. The key of this process is C which outputs G signal.
Two other CCs that output B and R signals to CD
Where D is attached by shifting it by 1/2 pixel in the horizontal direction, the processing of the G signal produces data for complementing the middle of the pixel adjacent to the pixel of the G signal, and the B signal and R output from the two CCDs. Signals are used to process the B and R signals, where the output of the CCD that outputs the G signals is used to create data between adjacent pixels, except when the three primary colors are imaged. Complementary data with no practical problems can be obtained.

In order to perform this so-called pixel shift processing, the processor 23a which performs digital signal processing has A
The three primary color signals B, G and R output from the DCs 15a, 15b and 15c are input, the two primary color signals B and G are input to the processor 23b, and the two primary color signals R and G are input to the processor 23c. Primary color signals are input. In this way, the processors 23a, 23b and 2
CCDs 12a, 12b and 12 from each of 3c
Two types of digital signals relating to the output pixel data of c and the pixel data that complements between these pixels are extracted.

Digital signals (pixel data) of two systems each read from the processors 23a, 23b and 23c
Is supplied in parallel to the BLK adding circuits 28a, 28b and 28c to add the blanking signal BLK from the SSG 19 and then supplied to the DA converters (DAC) 29a, 29b and 29c, respectively, and the analog video signal (primary color Signal). These two analog video signals are supplied to multiplexers (MPX) 30a, 30b and 3
0c are input in parallel, and are alternately switched based on the timing pulse from the timing pulse generation circuit 26 and rearranged in series to be an analog video signal having a double rate, and the number of effective horizontal pixels is 1920 pixels. An analog video signal corresponding to is obtained.

The analog primary color signals serially extracted from the MPXs 30a, 30b and 30c are supplied to the synchronization adding circuits 31a, 31b and 31c, respectively, and S
The sync signal from the SG 19 is added, and the signals are output as analog color B, G, and R primary color signals. This primary color signal is generated into a luminance signal Y and two types of color difference signals Pb and Pr by a matrix circuit (not shown) in the subsequent stage and can be switched and output.

The microcomputer 27 is a man-machine interface and is operated by a person to operate the processor 23.
It controls the effect amount of the processing performed in a, 23b, and 23c, and is not directly related to the gist of the present embodiment.

Next, the functions of the processors 23a, 23b and 23c, which constitute the main part of this embodiment, will be described with reference to FIG. Each of the processors 23a, 23b and 23c has a data input register (D
IR), which is an 8-bit × 960-stage 1-word serial input 960-word parallel output shift register 231, 232, 233 having 8-bit parallel input ports, and a register file (960 words) having parallel input / output ports. R
F) 234 and data output register (DOR)
8 of 960 words parallel input and 1 word serial output
Shift register 235, 236 of bit × 960-stage configuration
Therefore, the configuration of the present embodiment is realized.

Two DIRs 231 to 233 may be provided when the pixel data is two inputs. Further, the register file 234 is not a mere register but also utilizes a function as a processor to create complementary data between pixels.

Next, the operation of the processor shown in FIG. 3 will be described. As described above, the digital primary color signals read out from the CCDs 12a, 12b and 12c and further analog-to-digital converted by the ADCs 15a, 15b and 15c are data of the DIR 231 of the corresponding processor 23a, 23b or 23c as video data. 8 bits are input in parallel to the input terminal DIN, and this video data is successively written in synchronization with the serial transfer clock applied in series to the serial write clock terminal SWCK when the write enable terminal WE has a predetermined logical value. 1
When written for a line, all 960 words are R simultaneously
It is transferred to F232.

The RF 232 has a processing element (PE) and can perform signal processing by a program, but here, first in first out (FI).
FO) storage function is used, and 960 parallel input data are temporarily stored, and then 960 words are parallelized in the order of D input.
Output to OR233.

The DOR 233 is a read enable terminal R.
The video data of 960 words written in parallel when E has a predetermined logical value is transferred to the serial read clock terminal SRCK.
Are sequentially read in series in synchronism with the serial transfer clock applied in series, and are sent out as video data in the same order as when input to the DIR 231.

As described above, in this embodiment, the write register DIR 231 and the read register DOR 231 are used.
Since 233 is independent, the write clock rate and the read clock rate can be set to different rates independent of each other. Here, when the high-definition video signal having 1035 effective scanning lines and 1840 effective horizontal pixels is generated and output, the write serial transfer clock and the serial transfer clock for reading are the serial transfer clocks for writing. Although it is 74.25 MHz, the serial transfer clock for reading is 71.145 as described above.
It is set to MHz.

The important function in this embodiment is DIR23.
1 and DOR 233, and RF 232 is an appendix and can be omitted. Further, when outputting a high-definition video signal with 1080 effective scanning lines and 1920 effective horizontal pixels, the processor 23
The write serial transfer clock and the read serial transfer clock of a, 23b, and 23c are the same 7
It is set to 4.25 MHz.

The relationship between the write side timing and the read side timing is determined by the phase relationship between the sync signal generated in the SSG 19 and the video data read from the processors 23a, 23b and 23c, respectively. In order to keep the phase stable, the phase comparator 24, the VCXO 25, and the timing pulse generation circuit 26
It is necessary to devise a PLL circuit consisting of 3 to increase the DC gain and increase the stability.

FIG. 4 shows a concrete circuit diagram of an embodiment of this PLL circuit. In the figure, an integrated circuit (IC) 41 is an IC that constitutes the phase comparator 24, and for example, a model name MC14046B of Nippon Motorola Co., Ltd. is used. This I
When a pulse as shown in FIG. 5 is input to the input terminals PCAi and PCBi, C41 outputs the output terminals LD and P.
A phase error signal as shown in FIG. 5 is output from C2 / o.

Here, the write side horizontal timing pulse is applied to the input terminal PCAi by the timing pulse generating circuit 1.
8 and the horizontal synchronizing pulse HD is input to the input terminal PCBi from the timing pulse generating circuit 44 that constitutes the timing pulse generating circuit 26, and a 3-state pulse having a width corresponding to the phase difference between them is a phase error. The voltage is output from the output terminal PC2 / o.

The phase error voltage has a waveform as shown by VCOin in FIG. 5 by removing unnecessary high frequency components by the loop filter 42 consisting of the capacitor, the resistor and the operational amplifier forming the voltage follower of FIG. Is input to the IC 43 that constitutes the VCXO 25, and the output oscillation frequency thereof is variably controlled.

Since the output oscillation signal of the VCXO 43 has a small amplitude, it is amplified by the IC 441 in the timing pulse generating circuit 44 which constitutes the timing pulse generating circuit 26 composed of a counter and a logic circuit and is a CMOS level rectangular wave signal. It is shaped and sent to the subsequent circuits. It should be noted that LC1 and LC2 are line filters for preventing electromagnetic interference to prevent high-frequency signals from leaking to other circuits or the outside. Further, an electric field capacitor inserted between the power supply and GND is also inserted in order to remove noise of the power supply.

The output rectangular wave of the IC 441 is divided by 1/2 by the flip-flop 442, and the repetition frequency is 3
After being converted to a 5.5725 MHz clock, it is further divided by 1/2 in the flip-flop 443 to 17.87M.
The frequency is changed to Hz and is input to each clock terminal of the flip-flop 444, the IC 445, and the flip-flop 446. The flip-flop 444 has an input clock and IC4.
The processor 23 based on the output pulse from 45
It outputs a pulse to be output to the read enable terminals RE of a, 23b, and 23c.

The IC 445 is a digital IC which is composed of a counter and a comparator, and divides the frequency by 1/527 to output the horizontal synchronizing pulse HD of the horizontal scanning frequency and the DOR read start control signal of the processor to the flip-flops 446 and 444, respectively. Output to the data input terminal.
Flip-flops 446 and 444 are both ICs
It is a circuit having a function of re-timing for stabilizing the output signal of 445, and operates differently from the flip-flops 442 and 443.

With the PLL circuit having the above configuration, the IC 41
The detected phase error voltage of 1 is accumulated, and the feedback operation is performed so that the phase error becomes zero.
71.145MHz from O43 (25) (= 527 × 2
× 2 × Fh = 2108 × Fh: Fh is the horizontal scanning frequency)
Timing pulses are generated.

The timing pulse generation circuit 2 of FIG.
6 to DAC 29a to 29c and MPX 30a to 30c
The signal output to each of the inverters is delayed by an inverter and a delay in the substrate in which the processors 23a, 23b and 23c of FIG. 1 are placed based on the signal SRCK selectively output from the output terminal of the flip-flop 442 of FIG. 4 by the resistors R1 and R2. The timing is adjusted by the line.

As described above, according to this embodiment, one kind of general-purpose CCD is used to supply one of the two kinds of high-definition video signals without using a dedicated multi-pixel CCD, and at least the internal It is possible to generate and output by an inexpensive configuration provided with only the necessary system conversion circuit.

Next, a second embodiment of the present invention will be described. FIG. 6 shows a second television camera device according to the present invention.
FIG. 2 shows a block diagram of an embodiment. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and their description will be omitted. The second embodiment shown in FIG. 6 is the processor 2 of the first embodiment shown in FIG.
A pair of registers 53 is provided in front of 3a, 23b and 23c.
a and 54a, 53b and 54b and 53c and 54
c, the first switches 51a, 51b and 51c, the second switches 52a, 52b and 52c, and the third switches 55a, 55b and 55c.

The first and second switches 51a to 51c and 52a to 52c use the serial transfer clock of the registers 53a to 53c and 54a to 54c, respectively, using the output pulse of the write side timing generator or the output of the read side timing generator. It is a switch that switches whether to use a pulse. The registers 53a to 53c and 54a to 54c are line memories having a shift register function of 8-bit 960 stages. The third switches 55a to 55c are switches that switch the outputs of the registers 53a to 53c and 54a to 54c.

Next, the operation of this embodiment will be described.
Digital primary color signals obtained by analog-to-digital conversion by the ADCs 15a, 15b and 15c respectively are provided with corresponding one of the registers 53a, 53b.
And 53c to the 8-bit parallel input terminals, and
It is supplied to the 8-bit parallel input terminals of the other registers 54a, 54b and 54c.

At this time, when the first switches 51a, 51b and 51c are respectively connected to the upper terminals in FIG. 6, the write side shift pulse from the timing pulse generation circuit 18 is applied to the first switches 51a, 51b. And 51c to the registers 53a, 53b and 53c, thereby register 53a, 53b and 53c.
After the digital primary color signal of 960 pixels for one line is written in c, the writing side shift pulse is stopped.

Subsequently, the first switches 51a, 51b and 51c are connected to the lower terminals by switching as shown in FIG. 6, and the second switches 52a, 52b and 52c and the third switch 55a are connected. , 55b and 55c
Are connected to the upper terminals, respectively, as shown in FIG. As a result, the digital primary color signals of 960 pixels for one line written in the registers 53a, 53b and 53c are in a state of being read by the read side shift pulse from the timing generation circuit 26, and the read digital primary color signals are respectively. Third switch 55
a, 55b and 55c through processors 23a, 23
b and 23c respectively.

On the other hand, the registers 54a, 54b and 54c
The write side shift pulse from the timing pulse generating circuit 18 is supplied to the second switches 52a, 52b and 52c.
Since it is supplied through the digital primary color signal, the digital primary color signal can be written. Writing by the registers 54a, 54b, and 54c is controlled by the timing pulse generation circuit 18 in accordance with the read timing of the CCDs 12a to 12c.

When generating and outputting a high-definition video signal having 1035 effective scanning lines and 1840 effective horizontal pixels, the serial transfer clock for writing is 74.25 MHz, but the serial transfer clock for reading is As described above, since the transmission rate is 71.145 MHz, the write side and the read side have different transmission rates, but a part of the data on the read side is discarded and replaced by the blanking period. Further, since the horizontal scanning period on the writing side is the same as the horizontal scanning period on the reading side, the first to third switches 51a to 51c and 52a to 5 are included in the blanking period.
2c and 55a to 55c are switched.

Therefore, in the next blanking period, the first switches 51a, 51b and 51c are switched and connected to the upper terminals in the figure, and the second switches 52a, 52b and 52c and the third switch are connected. Switch 55
a, 55b and 55c are respectively switched and connected to the lower terminals in the figure, and the write side shift pulse is supplied from the timing pulse generating circuit 18 to the registers 53a, 53b and 53c, so that the digital primary color signals can be written. Then, the read side shift pulse from the timing pulse generating circuit 26 is supplied to the registers 54a, 54b and 54c, and the digital primary color signal can be read. Hereinafter, the above operation is repeated.

The present embodiment is slightly more complicated than the first embodiment if it includes the pixel complementary processing by pixel shifting, but
This is a method of independently performing screen aspect ratio conversion and pixel complementing processing, and the functions can be clearly separated accordingly. According to the second embodiment of FIG. 6, in the screen aspect ratio conversion unit, the first PLL circuit (16, 17, 18, 20) and the second PLL circuit (2
4, 25, 26), but differs from the first embodiment in that only the output signal of the second PLL circuit is used in the signal processing after the aspect ratio conversion.

In this embodiment, the write clock pulse SWCK of the processors 23a, 23b and 23c is generated by shifting the phase of the output clock pulse SRCK of the timing pulse generation circuit 26 by the delay circuit,
The write enable signal WE is the read enable signal R
The value of the counter is monitored and created in the same manner as in E, and the master clock MCK produces 1 / clock pulse SRCK.
It is generated by dividing the frequency by 2 or less.

As a result, this embodiment can also generate and output a high-definition video signal in which each pixel has a square shape with an inexpensive structure as in the first embodiment.

Next, a third embodiment of the present invention will be described. FIG. 7 shows a third example of the television camera device according to the present invention.
FIG. 2 shows a block diagram of an embodiment. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and their description will be omitted.

The third embodiment shown in FIG. 7 corresponds to the first embodiment shown in FIG.
Instead of the sync signal generator (SSG) 19 of the embodiment, a sync for generating a horizontal sync signal, a vertical sync signal and a blanking signal based on an output signal of a VCXO 25 which constitutes a PLL circuit for generating a timing pulse on the read side. A signal generator (SSG) 61 is provided. In addition,
The SSG 61 is reset by the vertical sync signal in the external sync signal. This embodiment also performs the same operation as each of the above embodiments.

Next, a fourth embodiment of the present invention will be described. FIG. 8 shows a fourth example of the television camera device according to the present invention.
FIG. 2 shows a block diagram of an embodiment. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and their description will be omitted.

The fourth embodiment shown in FIG. 8 corresponds to the first embodiment shown in FIG.
This is an embodiment in which the order of the two PLL circuits of the embodiment is reversed. That is, the horizontal sync signal or the vertical sync signal separated from the external sync signal is input to the phase comparator 67 and the timing pulse generation circuit 69 of the read side PLL circuit including the phase comparator 67, the VCXO 68 and the timing pulse generation circuit 69, respectively. The output timing pulse of the timing pulse generation circuit 69 is supplied to the DACs 29a to 29c, while being supplied to the phase comparators 64 and 67 and the timing pulse generation circuit 66.

The phase comparator 64 constitutes a write-side PLL circuit together with the VCXO 65 and the timing pulse generation circuit 66. From the timing pulse generation circuit 66, the sample and hold circuits 13a, 13b and 13c,
Pre-processing circuits 14a, 14b and 14c, ADC 15a,
Timing pulses are supplied to 15b and 15c, respectively, and a write clock, a write enable signal and a master clock are supplied to the processors 23a, 23b and 23c.

Further, the sync signal generator (SSG) 63 is V
A horizontal synchronizing signal, a vertical synchronizing signal, and a blanking signal are generated based on the output signal of the CXO 68. This embodiment is essentially the same as each of the above-described embodiments except that the PLL circuit for synchronizing the external synchronizing signal first is reversed, and has the same features as the above-mentioned embodiments.

FIGS. 9A and 9B show P corresponding to the second PLL circuit when the aspect ratio of the screen is 3: 4.
In the embodiment of the LL circuit, FIG. 10A shows a case where the reading in the vertical direction of the screen is 1035 scanning lines, and FIG.
In the circuit diagram when the number of scan lines is 0, the same components as those in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.

In the circuit shown in FIG. 9A, when the number of effective horizontal scanning lines is 1035, the number of effective horizontal pixels is 690 (=
1035 × 4/3/2) pixels, the total number of horizontal output pixels of the CCD is 960 pixels, and the total number of pixels is 27 from both ends of the screen.
Various timing pulses are generated to perform processing of discarding 0 pixels and time-extending the rest.

In this case, the first PLL circuit is 2200 ×
Since it oscillates at Fh, the second PL shown in FIG.
The VCXO 71 of the L circuit has a horizontal scanning frequency Fh of 158.
Oscillation is performed at an integer of 1582 times, which is close to 1.25 (= 2200 × 1380/1920) times. Therefore, VCXO71
The output oscillation frequency of is divided into 1/1582 by the 1/2 divider 442, the 1/7 divider 72, and the 1/113 divider composed of the ICs 73 and 74 to obtain the horizontal scanning frequency Fh. It is input to the phase comparator IC41. In this way, VCXO71 to 53.3925MHz
A pulse of (= 1582 × Fh) is output.

In the circuit shown in FIG. 9B, when the number of effective horizontal scanning lines is 1080, the number of effective horizontal pixels is 720 (=
Since the number of horizontal output pixels of the CCD is 960, a total of 24
Various timing pulses are generated to perform processing of discarding 0 pixels and time-extending the rest.

In this case, the first PLL circuit is 2200 ×
Since it oscillates at Fh, the second PL shown in FIG.
VCXO81 of L circuit is 1650 of horizontal scanning frequency Fh
Oscillate at (= 2200 × 1440/1920) times.
Therefore, the output oscillation frequency of the VCXO 81 is 1/1650 as a whole by the 1/2 divider 442, the 1/5 divider 82, and the 1/165 divider composed of the ICs 83 and 84.
The frequency is divided into the horizontal scanning frequency Fh and the phase comparator IC
41 is input. In this way, the VCXO 81 outputs a pulse of 55.6875 MHz (= 1650 × Fh).

[0080]

As described above, according to the present invention,
Digital video signal writing and reading are performed independently, and a video signal with a desired number of effective scanning lines is generated with a desired number of effective horizontal pixels even if the number of effective horizontal pixels is less than the number of effective horizontal pixels of the image signal targeted by the image sensor. When the target television standard is N effective scanning lines, the number of effective horizontal pixels is M pixels (M is an even number), and the aspect ratio of the screen is a: b, one type of image sensor ( CCD), the number of effective horizontal pixels is M, and the number of effective scanning lines is (M × a / b),
Alternatively, if the number of effective scanning lines is N, the number of effective horizontal pixels (N × b /
a) It is possible to generate and output a high-definition video signal in which the number of effective scanning lines and the number of effective horizontal pixels in which each pixel such as a pixel has a square shape is plural.

Further, according to the present invention, since only the required system conversion is performed by the digital signal conversion circuit, the configuration can be made cheaper than the conventional device equipped with the system conversion circuit for performing various system conversions, and various methods can be used. It contributes to the development of a good image culture.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between the number of effective horizontal pixels and the number of effective horizontal scanning lines according to the present invention.

FIG. 3 is a block diagram illustrating functions of the processor of FIG.

4 is a specific circuit diagram of an embodiment of the PLL circuit of the main part of FIG.

5 is a timing chart for explaining the operation of the main parts of FIG.

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is a block diagram of a third embodiment of the present invention.

FIG. 8 is a block diagram of a fourth embodiment of the present invention.

FIG. 9 is a concrete circuit diagram of each embodiment of the second PLL circuit of the essential part of the present invention.

FIG. 10 is a diagram illustrating a relationship between a CCD image pickup example and a screen display example according to the embodiment of the present invention.

[Explanation of symbols]

11 Prism 12a, 12b, 12c Charge Coupled Device (CCD) (Imaging Device) 13a, 13b, 13c Sample and Hold (S &
H) circuit 15a, 15b, 15c AD converter (ADC) (AD
Conversion means) 16, 64 first phase comparator (first timing pulse generation means) 17, 65 voltage controlled crystal oscillator (VCXO) (first
Variable frequency oscillator) 18, 66 First timing pulse generation circuit (first timing pulse generation means) 19, 61, 63 Synchronous signal generator (SSG) (analog video signal output means) 20 Timing generator (first Timing pulse generating means) 21 driving circuit (driving means) 23a, 23b, 23c processor (digital signal processing means) 24, 67 second phase comparator (second timing pulse generating means) 25, 68 voltage control type crystal Oscillator (VCXO) (Second
26, 69 second timing pulse generation circuit (second timing pulse generation means) 29a, 29b, 29c DA converter (DAC) (analog video signal output means) 30a, 30b, 30c multiplexer (MPX) )
(Analog video signal output means) 31a, 31b, 31c Synchronous signal addition circuit (analog video signal output means) 51a, 51b, 51c First switch (digital signal processing means) 52a, 52b, 52c Second switch (digital signal) Processing means) 53a, 53b, 53c, 54a, 54b, 54c Registers (digital signal processing means) 55a, 55b, 55c Third switch (digital signal processing means) 231, 232, 233 Data input register (DIR) 234 register file (RF) 235, 236 Data output register (DO
R)

Claims (7)

[Claims] 1. An AD conversion means for converting a video signal obtained by picking up an image by an image pickup device having a number of horizontal pixels smaller than a target number of effective horizontal pixels into a digital signal, and synchronizing with an external horizontal synchronizing signal. A first timing pulse generating means for generating and outputting the generated timing pulse; a driving means for driving the image pickup device with a drive signal output from the first timing pulse generating means; and a first timing pulse generating means Receiving the output first timing pulse as an input signal,
Second timing pulse generating means for generating a second timing pulse in synchronism with the second timing pulse, and the output digital signal of the AD converting means is written based on the first timing pulse, and the written digital signal is written as the digital signal. Digital signal processing means for reading out based on the second timing pulse, and a digital signal read out from the digital signal processing means for converting into an analog signal based on the second timing pulse, and at the same time by the pixel shifting technique. A television camera device, comprising: an analog video signal output means for generating and outputting a video signal having a desired number of effective horizontal pixels and having a composite synchronizing signal added thereto. 2. The first timing pulse generating means outputs an output oscillation frequency according to a first phase comparator to which the external horizontal synchronizing signal is input and an output phase error voltage of the first phase comparator. A first variable frequency oscillator that is variably controlled, a timing generator that divides the output signal of the first variable frequency oscillator to generate the drive signal, and various types of the above based on the output signal of the timing generator. A first PLL circuit including a first timing pulse generating circuit for generating a first timing pulse and feeding back a signal of a horizontal scanning frequency to the first phase comparator; The second timing pulse generating means includes a second phase comparator to which the first timing pulse from the first timing pulse generating circuit is input, and a second phase comparator. A second variable frequency oscillator whose output oscillation frequency is variably controlled by a force phase error voltage, and which divides an output signal of the second variable frequency oscillator and generates various second timing pulses, and The second PLL circuit is composed of a second timing pulse generating circuit for feeding back a part of the second timing pulse to the second phase comparator to compare the phase with the first timing pulse. The composite sync signal added by the analog video signal output means is reset by an external vertical sync signal and is generated based on the output signal of the first or second variable frequency oscillator. The television camera device according to claim 1. 3. The first timing pulse generating means includes a first phase comparator and a first variable frequency oscillator whose output oscillation frequency is variably controlled by an output phase error voltage of the first phase comparator. A timing generator that divides the output signal of the first variable frequency oscillator to generate the drive signal; and various first timing pulses that are generated based on the output signal of the timing generator; , A first PLL circuit comprising a first timing pulse generating circuit for feeding back a signal of horizontal scanning frequency to the first phase comparator, and the second timing pulse generating means, A second phase comparator to which an external horizontal synchronizing signal is input;
A second variable frequency oscillator whose output oscillation frequency is variably controlled by an output phase error voltage of the phase comparator of
Divides the output signal of the variable frequency oscillator, and generates various kinds of the second timing pulses; and
A second timing pulse generating circuit for feedback-inputting a part of each of the timing pulses to the first and second phase comparators for phase comparison with the first timing pulse and the external horizontal synchronizing signal, respectively. Become the second P
The composite synchronizing signal which is composed of an LL circuit and which is added by the analog video signal output means is reset by an external vertical synchronizing signal and is generated based on the output signal of the second variable frequency oscillator. The television camera device according to claim 1, wherein: 4. The processor, wherein the digital signal processing means writes the output digital signal of the AD conversion means based on the first timing pulse and reads the written digital signal based on the second timing pulse. The television camera device according to claim 1, further comprising: 5. The digital signal processing means includes the A
The first timing pulse is applied as a write shift pulse to the first and second registers to which the output digital signals of the D conversion means are simultaneously input, and one of the first and second registers, and the other of them is applied. Register the second
Of the first and second switches for alternately switching the input of the write shift pulse and the read shift pulse to the first and second registers, while applying the timing pulse as the read shift pulse. A third switch that selects the output of one of the two registers to which the read shift pulse is input and an output digital signal of the third switch are written and written based on the first timing pulse. 2. The television camera device according to claim 1, further comprising a processor for reading the digital signal generated based on the second timing pulse. 6. When the target television standard is N effective scanning lines, the number of effective horizontal pixels is M pixels (M is an even number), and the aspect ratio of the screen is a: b, the image sensor is effective in scanning. 6. The television camera device according to claim 1, wherein the number of lines is (M × a / b) and the number of effective horizontal pixels is M / 2 pixels. 7. When the target television standard is N effective scanning lines, the number of effective horizontal pixels is M pixels (M is an even number), and the aspect ratio of the screen is a: b, the image sensor is effective in scanning. The number of lines is (M × a / b) and the number of effective horizontal pixels is M / 2 pixels. The second timing pulse generating means outputs the second pulse to the digital signal processing means as a read pulse. The frequency of the timing pulse is {N / (M ×) to the frequency of the first timing pulse applied as a write pulse to the digital signal processing means.
a / b)} is set to a frequency that is a natural number multiple of the horizontal scanning frequency that is closest to the multiplied value and an analog video signal of effective horizontal pixels (N × b / a) pixels is generated and output with N effective scanning lines. The television camera device according to claim 1, wherein: