JP3253451B2 - Composite sync signal delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite synchronizing signal delay circuit for delaying a composite synchronizing signal containing both a horizontal synchronizing signal and a vertical synchronizing signal by a predetermined time.

[0002]

2. Description of the Related Art In a television signal, a horizontal / vertical synchronizing signal is superimposed on a video signal, and when performing various processes on the video signal, the synchronizing signal is separated and then performed.
Therefore, it is necessary to superimpose the synchronization signal again after various processes, and a synchronization signal synchronized with the input television signal is required. The video signal is often subjected to delay processing in the processing, and in such a case, the synchronizing signal superimposed on the video signal must be similarly delayed. Therefore, a delay circuit for delaying a synchronization signal is required, and a delay circuit using a glass delay line (delay line) or a CCD (charge coupled device) is conventionally known.

[0003]

However, the glass delay line has a problem that the delay amount cannot be increased so much that the glass delay line is not suitable for, for example, a delay of one horizontal line (1H). Also, in the case of using a CCD, the longer the delay time, the more elements are required, and there is a problem that the device becomes large and expensive.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a composite synchronization signal delay circuit which can obtain a large delay time with a relatively simple device. And

[0005]

SUMMARY OF THE INVENTION The present invention is a delay circuit for a composite synchronizing signal including both a horizontal synchronizing signal and a vertical synchronizing signal, and detects a low level of the composite synchronizing signal and synchronizes with the low level. A sync separation circuit that obtains a composite separation signal having a pulse, detects a vertical synchronization signal from a difference in length of a low-level period, and obtains a vertical separation signal having a pulse synchronized with the synchronization signal, and a composite obtained by the synchronization separation circuit H which is reset by the separation signal and counts a predetermined reference clock, for example, 4 fsc
The output of the counter and the H counter is decoded, a signal whose level changes in accordance with the count value of the H counter is output, and a plurality of signals having different duty ratios can be generated as the output signals. , A V counter that is reset by the vertical separation signal and counts the composite separation signal, decodes the output of the V counter, and selects one of the H decoder according to the count value of the V counter. And a V-decoder for controlling whether or not to generate a composite signal, and by setting a signal generated from the H-decoder in accordance with the count value of the V-counter, a composite synchronization signal with an arbitrary delay time It is characterized by obtaining.

Further, the field determination circuit determines whether the first field or second field from the position of the horizontal synchronizing signal for vertical synchronization signal, based on the determination result of the field determination circuit, a composite separation to be input to the V counter Signal , a horizontal synchronizing signal portion in the first field
And a gate circuit for masking one-half pulse. A composite signal for one frame is generated by making the generated signals from the H decoder selected by the count value of the V counter the same in the first and second fields. It is preferred to do so .

[0007]

As described above, according to the present invention, the decoding content of the H decoder is switched according to the count value of the V counter, whereby a plurality of types of signals are obtained from the output of the H decoder. That is, the H decoder can output three types of waveforms, a vertical synchronizing signal, an equivalent pulse, and a horizontal synchronizing signal, and selects one of them according to the count value of the V counter. By setting the selection order to a predetermined order, a composite synchronization signal for one frame can be obtained. Therefore, by changing the relationship between the count value of the V counter and the selection of the waveform by the H decoder, a composite synchronization signal having an arbitrary delay time can be obtained. In particular, even if the delay time is relatively long such as 1H, the circuit configuration is simple and a reliable delayed signal can be obtained.

Further, the field judgment circuit judges the field and applies a predetermined mask to the clock inputted to the V counter, so that the waveforms of the first and second fields can be counted by the V count value and decoded by the H decoder. The relationship can be obtained with the same relationship.
By blocking the input of one pulse of the composite separation signal (one pulse of the horizontal synchronization signal portion) to the V counter in the first field, the count value of the V counter can be shared.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

[Overall Configuration] FIG. 1 is a block diagram showing the overall configuration of the embodiment. The input composite sync signals CSYNC0 and 4fsc clock are input to the sync separation circuit 10. Here, the 4fsc signal is a signal having a frequency four times the frequency fsc (3.58 MHz) of the color subcarrier. The synchronization separation circuit 10 generates a composite separation signal CSYNCEP which is a pulse signal corresponding to the fall of the composite synchronization signal CSYNC0, and a vertical separation signal VSEP which is a pulse signal corresponding to the fall of the vertical synchronization signal VSYNC. Here, VSEP
Is detected using the fact that the L period of VSYNC is sufficiently longer than the equivalent pulse and the horizontal synchronization signal HSYNC.

[0011] The CSYNCEP from the sync separation circuit 10
Is supplied to the H counter 12 as a reset pulse. The H counter 12 is supplied with 4 fsc as a clock. The H counter 12 counts up 4 fsc, and the count value is reset by CSYNCEP. The count value of the H counter 12 is supplied to the H decoder 14, and when the count value of the H counter 12 reaches a predetermined value, the H decoder 14 changes from L to H.
Is output. This output becomes the delay signal CSYNC.

Also, CS which is the output of the sync separation circuit 10
YNSEP is input to the V counter 18 via the gate 16. The V counter 18 is also supplied with VSEP, which is the output of the sync separation circuit 10, and counts up CSYNCEP, and the count value is reset by VSEP. A V decoder 20 is connected to the output of the V counter 18, and supplies a control signal to the H counter 12 according to the count value of the V counter 18. That is, the decoding of the H decoder 14 is controlled in accordance with the count value of the V counter 18, and the output of three types of waveforms is switched.

The output of the V decoder 20 is supplied to a field determination circuit 22. The field determination circuit 22 includes an input composite synchronization signal CSYNC0, VSYNC
A signal VCLK obtained by dividing SEP and 4fsc by 64, for example.
Is supplied. This VCLK is obtained by dividing 4fsc by the frequency divider 2
The signal is divided by 64 and divided by 64, and has a period of 4.5 μsec. Then, the field determination circuit 22 generates a signal JFIELD for controlling the gate 16 by identifying the first field and the second field from these signals. Then, the gate 16 is connected only during the period when this JField is H,
The output of CSYNCEP is inhibited from being input to the V counter 18. This allows the first field and the second
In both fields, the operation of the H decoder can be controlled based on the same count value of the V counter 18 to obtain the CSYNC signals of the first and second fields having HSYNCs with different timings.

Next, the operation of this circuit will be described with reference to FIG. Since a television signal performs interlaced scanning, one screen (one frame) is composed of two fields, the last horizontal scanning line of the first field ends in the middle of the screen, and the first horizontal scanning of the second field. The line starts in the middle of the screen. Accordingly, the two horizontal scanning periods are H / 2 (where H indicates the horizontal scanning period), and the timing of the horizontal scanning line is shifted between the first field and the second field.

That is, as shown in FIG. 2, one frame is composed of a horizontal scanning period of 525H. And 3H × 2 = 6H vertical pulses. Assuming that the start of the vertical synchronization pulse (when a pulse is generated in VSEP) is “0”, a normal horizontal synchronization signal starts from the 6H.

The first field has a period of 1H from the horizontal synchronization signal of the 6H, and the last horizontal scanning ends in half of the 259H, and the period is of the period of H / 2. ing. The normal horizontal synchronizing signal of the second field starts from 269H.

Then, the synchronization separation circuit 10 detects a vertical synchronization period and generates a vertical separation signal VSEP. VSEP
Is detected because the L period is long, so the generation timing is slightly delayed. However, this deviation can be compensated for in various processes, and there is no problem in the overall process.

The composite separation signal CSYNCE
P is output every time CSYNC0 falls. In this manner, VSEP and CSYNCEP as shown in the figure are obtained in the sync separation circuit 10.

In the apparatus of the present embodiment, the V counter 18 is reset by VSEP and the CSY is reset.
Count NSEP. That is, the V counter 18
Counts the CSYNCEPP pulse output each time the horizontal / vertical synchronization signal and the equivalent pulse fall. However, CSYNCEP to the V counter 18
A gate circuit 16 is arranged on the input path of the first field, and this gate circuit 16 masks one pulse of the first field. In this example, counting is started from the vertical synchronizing signal, and the 13th CSYNCEP corresponding to the end edge of the first horizontal scanning line that has entered the horizontal synchronizing signal is masked.

As described above, the count value of the V counter 18 becomes a value as shown immediately below CSYNCEP in the figure, and takes a value of 0 to 271 in both the first field and the second field. And this V counter 1
The H decoder 14 is controlled by the count value of eight.

That is, the H counter 12 outputs the CSYNC
Reset by 0 and count 4fsc. In this case, the H counter 12 counts from 0 to 910 during the 1H period. Then, from the H decoder 14, CSYN
C must be generated, and it is necessary to output three types of waveforms: a vertical synchronization signal, an equivalent pulse, and a vertical synchronization signal. Therefore, the H decoder 14 decodes the count value of the H counter 12 and obtains three types of outputs as shown in FIG. That is, (A) for vertical synchronization signal: 0 to 38
6 is L, 387 to 909 are H, (B) for equivalent pulse: 0
33 to L, 34 to 909 are H, (C) for horizontal synchronizing signal: 0 to 67 output L waveforms, and 68 to 909 output H waveforms.

Then, the count value 0 of the V counter 18 is
5, 271 (A) for vertical synchronization signal, 6 to 11, 2
At the time of 65 to 270 (B) for equivalent pulse, 12 to 264
At the time of (C), by performing decoding for the horizontal synchronization signal, it is possible to obtain CSYNC having the same (delay time 0) as CSYNC0.

With such a setting, in the case of the first field, the vertical synchronization signal (A) is generated from the count value 271 of the V counter 18 and is reset by CSYNCEP with the count value 455 of the H counter 12. Therefore, a vertical synchronization signal is generated until the count value reaches 5. Next, during the period of the count values 6 to 11 of the V counter 18, an equivalent pulse is generated by the equivalent pulse (B). Also in this case, the count value 455 of the H counter 12 is
SYNCEP is input, and the count value is reset.

Thereafter, the count value 12 of the V counter 18 is
In 〜264, a horizontal synchronization signal is generated. In this case, H
The counter 12 is not reset until the count value 910. When the count value of the V counter 18 is 264, CSYNCEP is input in a half cycle (count value 455 of the H counter 12) and reset. Therefore, the horizontal scanning period at this time is a period of H / 2. The 13th pulse of CSYNCEP is gate 1
6 prevents it from being input to the V counter 18.

In the case of the second field, when the count value of the V counter 18 is 11, CSYNCEP is not input in a half cycle (the count value 455 of the H counter 12).
Therefore, at this time, H of the equivalent pulse continues for the subsequent half cycle. Then, a horizontal synchronization signal is output thereafter.

As described above, according to this embodiment, the relationship between the count value of the V counter 18 and the output waveform of the H decoder 14 is obtained by not inputting the 13th pulse of CSYNCEP in the first field to the V counter 18. The synchronization signal corresponding to the first and second fields can be automatically obtained without any change.

In the above description, the H decoder 14
Is output at the same timing as CSYNC0. However, when this signal is to be delayed, (A) and (B) of the H decoder 14 based on the value of the V counter 18 are used.
What is necessary is just to change the correspondence of the selection of (C). For example, the count values 2 to 7, 2 of the V counter 18 are (A), 8 to 13,
267-1 as (B) and 14-266 as (C),
By adding 2 to all, 1H delayed CS
YNC can be obtained. Note that the gate circuit 16
In the same manner as described above, the
CSYNCEP at the end edge of the second horizontal scan line
And it is sufficient.

[Configuration of Sync Separation Circuit 10] FIG. 4 shows an example of a circuit for generating CSYNCEP in the sync separation circuit 10. This circuit comprises two flip-flops 32, 3
4 and one inverter 36 and one AND gate 38. CSYNC0 is input to the D input of the flip-flop 32, and the signal A, which is the Q output of the flip-flop 32,
4 is input to the D input. 4fsc is input to the C input of the flip-flops 32 and 34. Then, three signals, that is, the inverted Q output of the flip-flop 32, the Q output of the flip-flop 34, and a signal that determines 4fsc by the inverter 36, are input to the AND gate 38, and the output becomes CSYNCEP.

That is, as shown in FIG. 5, the flip-flop 32 causes the D input C
Capture SYNC0. Therefore, when CSYNC0 falls, the next rising of 4fsc causes this CSYNC to rise.
L of NC0 is taken into the flip-flop 32, the output A becomes L, and the inverted Q output becomes H. On the other hand, the output of the flip-flop 34 remains at H until the next rise of 4fsc. When a half cycle of 4fsc elapses, 4fsc
sc becomes L for a half cycle, and the inverted 4fsc inverted by the inverter 36 becomes H during that period. Therefore, all the inputs to the AND gate 38 become H, and the CSYNCEP which becomes H during the half period of L of 4 fsc is output from the AND gate 38.

As described above, the circuit shown in FIG.
CSYNCSEP can be obtained by cutting out the falling edge of NC0. Note that R of the flip-flops 32 and 34
A reset signal RESET is input to the input so that the stored contents are reset when the power is turned on.

VSEP is the signal A or B
Is measured using a counter or the like, and it may be detected that this period is sufficiently longer than the period of L of the horizontal synchronization signal or the equivalent pulse. In this case, the counter used for counting the clock obtained by dividing the frequency of 4 fsc requires a smaller number of bits. For example, VCLK in the field determination circuit 22 to be described later may be used, and the counter itself may also be used in the field determination circuit 22.

[Configuration of Field Determination Circuit] FIG. 6 shows an example of the field determination circuit 22. The output of the AND gate 20a, which is one internal circuit of the V decoder 20, is input to the C input of the flip-flop 42. In this example, the AND gate 20a outputs H when the count value of the V counter 18 is 11. This flip-flop 4
The D input of No. 2 is always suspended at H. The Q output of the flip-flop 42 is input to the counter 44 as an L active reset signal. The counter 44 is supplied with a signal VCLK having a period of 4.5 μsec obtained by dividing 4 fsc in the frequency divider 24, for example, by 64 as a clock.

In this example, the counter 44 has three outputs, and outputs H when the count value has three values of "5", "11", and "12". Counter 44
Are output to the S and R inputs of the RS flip-flop 46, respectively. Therefore, H is set in the RS flip-flop 46 while the count value of the counter 44 is "5" to "11". The output of the RS flip-flop 46 is input to the D input of the flip-flop 48. This flip-flop 48 has CSYNC0 input to its C input.
A signal JFIELD is output from the Q output. Further, VSEP is input to the L-active reset terminal of the flip-flop 48, and the contents are reset when VSEP is H.

Further, the “12” output of the counter 44 is input to the NOR gate 50. VSEP is also input to the NOR gate 50, and its output is input to the L-active reset terminal of the flip-flop 42. Therefore, the flip-flop 42 is reset by H of VSEP or the count value “12” of the counter 44.

Next, the operation of this circuit will be described with reference to FIG. First, when VSEP goes high, the flip-flop 42 is reset to low. Therefore, L is supplied to the reset terminal of the counter 44,
Does not count. When the count value of the V counter 18 becomes "11", the AND gate 20a outputs H
Is output and H is set in the flip-flop 42, so that the counter 44 starts counting VCLK. When the count value becomes "5", H is set in the RS flip-flop 46, and the count value becomes "11".
, The RS flip-flop 46 is reset to L. Then, the count value of the counter 44 is "5" to "1".
When CSYNC0 rises during the period of "1", H of the RS flip-flop 46 is taken into the flip-flop 48 at this rising.

Here, in the case of this example, VCLK is 4 fsc
Is divided by 64. Accordingly, 64 of the count value of the H counter 12 corresponds to 1 of the count value of the counter 44. Therefore, the count value of the counter 44 is 5-11.
Corresponds to the count values 320 to 704 of the H counter 12. Therefore, the RS flip-flop 46 outputs H near the middle of 1H. Then, in the first field, the twelfth pulse of CSYNCEP is output during this period, and H is taken into the flip-flop 48. The H of the flip-flop 48
Returns to L at the rise of CSYNC0. Therefore, H is output during 1H in JFIELD which is the output of the flip-flop 48. This JField
The H period includes the timing at which the thirteenth pulse of CSYNCEP is generated. So, this JFIE
By closing the gate 16 with H of LD, C
The 13th pulse of SYNSEP is not input to the V counter 18, and the count value of the V counter 18 becomes 1 at the time of the 14th pulse of CSYNCEP as shown in FIG.
It becomes 3.

On the other hand, in the case of the second field, CSYNCS
The twelfth pulse of the EP is 1H from the eleventh pulse.
Later. Therefore, H is not taken into the flip-flop 48, and JFIELD does not become H. Therefore, as shown in FIG. 2, all the pulses of CSYNCEP are counted, and the count of 0 to 271 is performed.

As described above, by using the field determination circuit 22 of the present embodiment, the count of CSYNC0 in the V counter 18 is changed between the first field and the second field, and the count value of the V counter 18 and the H decoder It is possible to make the relationship between the 14 decoding contents the same. Therefore, the entire circuit can be simplified.

[0039]

As described above, according to the present invention,
The decoding content of the H decoder is switched according to the count value of the V counter, whereby the output of the H decoder is obtained for a plurality of types of signals. That is, the H decoder can output three types of waveforms, a vertical synchronizing signal, an equivalent pulse, and a horizontal synchronizing signal, and selects one of them according to the count value of the V counter. By setting the selection order to a predetermined order, a composite synchronization signal for one frame can be obtained. Therefore, by changing the relationship between the count value of the V counter and the selection of the waveform by the H decoder, a composite synchronization signal having an arbitrary delay time can be obtained. In particular, even if the delay time is relatively long, such as 1H or several H, the circuit configuration is simple and a reliable delayed signal can be obtained.

Further, the field judgment circuit judges the field and applies a predetermined mask to the clock input to the V counter, so that the waveforms of the first and second fields can be counted by the V count value and decoded by the H decoder. The relationship can be obtained with the same relationship.
By blocking the input of one pulse of the composite separation signal (one pulse of the horizontal synchronization signal portion) to the V counter in the first field, the count value of the V counter can be shared.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an embodiment.

FIG. 2 is a diagram illustrating timings of signals separated in a synchronization separation circuit 10;

FIG. 3 is a diagram showing a relationship between a count value of a V counter and an output waveform from an H decoder.

FIG. 4 is a block diagram illustrating a main configuration of a synchronization separation circuit.

FIG. 5 is a diagram illustrating an operation of the synchronization separation circuit 10;

FIG. 6 is a block diagram showing a configuration of a field separation circuit 22.

FIG. 7 is a diagram illustrating the operation of the field separation circuit.

[Explanation of symbols]

 Reference Signs List 10 Sync separation circuit 12 H counter 14 H decoder 16 Gate 18 V counter 20 V decoder 22 Field judgment circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^5/ 04-5/12

Claims (2)

(57) [Claims] 1. A composite synchronizing signal delay circuit including both a horizontal synchronizing signal and a vertical synchronizing signal, which detects a low level of the composite synchronizing signal and obtains a composite separated signal having a pulse synchronized with the low level. A synchronous separating circuit for detecting a vertical synchronizing signal from a difference in length of the low-level period and obtaining a vertical separating signal having a pulse synchronized with the vertical synchronizing signal; An H counter that counts the reference clock, decodes the output of the H counter, outputs a signal whose level changes according to the count value of the H counter, and can generate a plurality of signals with different duty ratios as the output signal. And an H decoder that can select which signal to generate, and And a V-decoder for decoding the output of the V-counter and controlling which signal is generated in the H-decoder according to the count value of the V-counter. A composite synchronization signal having an arbitrary delay time at an output of the H decoder by setting a signal generated from the H decoder in accordance with a count value of a V counter. 2. The circuit according to claim 1, further comprising: from a position of the horizontal synchronization signal with respect to the vertical synchronization signal.
A field determination circuit determines whether the first field or the second field, based on the determination result of the field determination circuit, the first feature a composite separation signal input to the V counter
And a gate circuit for masking one pulse of a horizontal synchronizing signal portion in the field , wherein the signals generated from the H decoder selected by the count value of the V counter are the same in the first and second fields. A composite synchronizing signal delay circuit for generating a composite signal for one frame.