JPS63279681A - Video signal reader - Google Patents

Abstract

PURPOSE:To synchronize a sampling clock with a horizontal synchronizing signal and to reduce the jitter of a sampling by resetting a frequency dividing counter to generate the sampling clock at the timing of an internal horizontal synchronizing signal synchronizing with a reference clock. CONSTITUTION:A reference clock generating means 111 generates the reference clock (j) of a frequency 12 fsc. A synchronizing signal (k) switched by a synchronizing signal switching means 112 is made into the internal horizontal synchronizing signal (l) synchronizing with the (j) by an internal horizontal synchronizing signal generating means 113. A quarterly dividing counter 114 is reset by a reset signal generating means 115 at the signal (l). When the reset is released, the counter 114 quarterly dividing counts the (j), and generates the sampling clock (m). After the initial value (1FA) of an address is set in an address counter 116 at the signal (l) by a load signal generating means 117, the (m) is counted and a picture element address (s) is given to a memory 119 and an input signal (q) selected by an input signal selecting means 107 is A/D-converted at the timing of the (m) by an A/D converting means 118 and a picture element data (r) is recorded in the memory 119.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to means for generating a clock for sampling video signals, and is widely used in frame memories, hard copy devices for television screens such as image printers, etc. It is possible.

Conventional Example FIG. 3 is a block diagram showing a conventional example of a video signal reading device. This is the case when RGB signals or black and white signals are input. 301 is a sampling clock generation means; 3o2 is a M/D conversion means for converting the input video signal 'iA/D at the timing of this sampling clock; 303
memory means for recording Ham/D converted pixel data;
304 counts the sampling clock and stores the memory 30
3 is an address counter that provides a pixel address; 306 is an internal horizontal synchronization signal generating means for obtaining an internal horizontal synchronization signal synchronized with a sampling clock from an input horizontal synchronization signal;
306 is a load signal generating means for generating a signal for setting the initial value of the pixel address in the address counter from this internal horizontal synchronization signal, 307 is a terminal to which a video signal is input, and 308 is a terminal to which a synchronization signal is input. .

A sampling clock generation means 301 generates a sampling clock, and an internal horizontal synchronization signal generation means 305 synchronizes an input horizontal synchronization signal with this sampling clock to obtain an internal horizontal synchronization signal synchronized with 3 fsc. Then, the load signal generating means 306 generates a load signal at the timing of this internal horizontal synchronizing signal, and sets the initial value of the pixel address in the address counter 304. The horizontal scanning lines of pixel data subjected to Mu/D conversion by the Mu/D converter 302 in synchronization with an internal horizontal synchronizing signal are continuously written into the memory 303.

FIG. 4 shows a second conventional example of a video signal reading device. This input is an NTSC signal.

401 is a terminal to which an NTSG signal is input; 402 is synchronization separation means for separating a horizontal synchronization signal from the input NTSC signal; 403 is a burst gate pulse generation means for generating a burst gate pulse from the separated horizontal synchronization signal; 4o
4 is a burst gate means for extracting a burst signal from the input NTf30 signal using this burst gate pulse;
06 is a sampling clock generating means that generates a sampling clock with a frequency of 3 fsc (fsc is the color subcarrier frequency of the NTSG signal = 3.879545H2) in synchronization with this extracted burst signal, and 406 is an input device using this sampling clock. 407 is a memory for recording the pixel data subjected to the Mu/D conversion; 408 is an address counter that counts the sampling clock and provides a pixel address to the memory 407; 409 is a horizontal Internal horizontal synchronizing signal generating means 410 generates an internal horizontal synchronizing signal synchronized with the sampling clock from the synchronizing signal, and 410 is a load signal generating means generating a signal for setting the initial value of the pixel address in the address counter.

The horizontal synchronization signal is separated from the input NTSC signal by the synchronization separation means of 402, and from the separated horizontal synchronization signal, the 4o3
The burst gate pulse generation means generates a burst gate pulse, and the input N is generated by the burst gate means of 4o4.
Extract the burst signal from the TSC signal. In synchronization with the extracted burst signal, the sampling clock generation means 405 generates a sampling clock with a frequency of 3 fsc, and the internal horizontal synchronization signal generation means 409 synchronizes the input horizontal synchronization signal with the sampling clock.
Obtain an internal horizontal synchronization signal synchronized with fsc.

Then, the load signal generating means 410 generates a load signal at the timing of this internal horizontal synchronizing signal, and sets the initial value of the pixel address in the address counter 408. Mu/D
The conversion means 406 synchronizes with the internal horizontal synchronizing signal
The D-converted pixel data for the horizontal scanning line is continuously written into the memory 407 in order from the set pixel address.

Problems to be Solved by the Invention According to the method of the first conventional example, jitter of about one period of the maximum sampling clock occurs between the input horizontal synchronization signal and the internal horizontal synchronization signal, and the sampling point of the pixel The image will be shifted by about one pixel at most, and if the screen has vertical stripes, the vertical lines will be jittery and the image will be very dirty.

In addition, according to the second conventional example, since the phase of the burst signal is inverted every scanning line period, there is an fs difference between the human horizontal synchronization signal and the sampling clock every scanning line period.
Jitter for one cycle of c always occurs, and the pixel sampling point always shifts by 1/2 pixel, resulting in vertical lines on the screen becoming zigzag.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a video signal capture device with less sampling jitter.

Means for Solving the Problems In the present invention, in order to solve the above problems, the frequency fHz
a reference clock generating means, a frequency dividing counter means for dividing the frequency of this reference clock by -iN (N is an integer of 2 or more) and generating a sampling clock, and a mu/D converting the input video signal using the sampling clock. a conversion means;
The timing of the internal horizontal synchronization signal between an address counter that counts the sampling clock and generates a sampling pixel address, and an internal horizontal synchronization signal generation means that obtains a signal synchronized with tHz of the reference clock from the horizontal synchronization signal. a reset signal generating means for generating a signal for resetting the cycle counter means; and a load signal generating means for generating a signal for setting an initial value of a pixel address in the address counter at the timing of the internal horizontal synchronization signal, By resetting the frequency dividing counter that generates the sampling clock at the timing of an internal horizontal synchronization signal synchronized with the clock, the sampling clock is synchronized with the horizontal synchronization signal and sampling jitter is reduced.

The operational reference clock generation means generates a reference clock with a frequency of fHz, and the frequency division counter means divides the frequency of this reference clock by N (N is an integer of 2 or more) to generate a sampling clock. The A/D conversion means converts the input video signal into digital pixel data at the timing of the sampling clock.The zero address counter counts the sampling clock and generates a pixel address. The internal horizontal synchronization signal generation means generates an internal horizontal synchronization signal synchronized with fHz of the reference clock, and the reset signal generation means resets the frequency division counter at the timing of the internal horizontal synchronization signal, thereby changing the sampling clock to the internal horizontal synchronization signal. Also, the initial value of the pixel address is given to the address counter at the timing of the internal horizontal synchronization signal by the load signal generating means.

EXAMPLE An example of the present invention is shown in FIG. In this figure, 10
1 is a terminal to which a video signal a of R, 0 or B of an RGB signal is input, 1o2 is a terminal to which a horizontal synchronizing signal is input, 103 is a terminal to which an NTSC signal C signal is input, 104
outputs 1 only when RGB signals are input
GB signal detection means 106 is an NTSC signal detection means that outputs 1 only when an NTSC signal is input;
6 is the output d of the RGB signal detection means 104 and the output e of the NT8G signal detection means 106. If both signals are input, one of the preset signals is selected as either the RGB signal or the NTSC signal. switching signal generating means for outputting a signal f for selecting one of the input signals when either one is input;
07 is a video signal a,! by signal f. :NTSC signal C
108 is an input signal selection means for selecting either one of the signals; 108 is a synchronization separation means for separating the NTSC signal C signal power period signal;
Reference numeral 109 denotes a burst gate pulse generating means 1 for generating a burst gate pulse h from the separated horizontal synchronizing signal g.
1o is input NTSC by this burst gate pulse h.
A burst gate means 111 extracts a burst signal from the signal C, and when the switching signal f is a signal for selecting an NTSC signal, a reference clock j having a frequency of 12 fsc which is phase synchronized with the extracted burst signal 1 is connected to the switching signal f. When the signal selects an RGB signal, a reference clock generating means generates a reference clock j with a frequency of 12 fsc by free-running oscillation, 112 is a synchronous signal switching means for switching the synchronous signal by a switching signal f, and 113 is a synchronous signal k. internal horizontal synchronization signal generation means for generating an internal horizontal synchronization signal 1 synchronized with the reference clock; 114 is a 4-frequency division counter means for dividing the reference clock j by 4 and generating a sampling clock m=i with a frequency of 3 fsc; 115 is an internal Horizontal synchronization signal 1
116 is an address counter that counts the sampling clock mi and generates an address S. 117 is an address counter that generates an address to the address counter 116 at the timing of internal horizontal synchronization signal 1. The initial value of (IF
Load signal generating means for generating a signal for all settings, 1
18 is input signal q selected by input signal selection means 107 and is input to M/D at the timing of sampling clock m.
Mu/D conversion means for converting into pixel data r, 119
is a memory means for recording pixel data rl using a pixel address S.

FIG. 2 shows a timing diagram of each part of this embodiment.

The reference clock generating means 111 generates a reference clock 1 having a frequency of 12 fsc. The internal horizontal synchronizing signal generating means 1 is used for the synchronizing signal switched by the synchronizing signal switching means 112.
13 becomes an internal horizontal synchronization signal l synchronized with 12 fsc of the reference clock j.

The internal horizontal synchronization signal l is generated by the reset signal generation means 116.
The 4-frequency division counter 114 is reset at the timing of .

When the reset is released, the frequency division counter 114 divides the frequency of the reference clock by 14, and generates a sampling clock mi having a frequency of 3 fsc. Load signal generating means 117
After setting the initial address value (1F person) to the address counter 116 at the timing of the internal horizontal synchronization signal 1, the sampling clock! +1 is counted and given to the pixel address s'1 memory 119, and the M/D conversion means 118
The input signal q selected by the input signal selection means 107 is subjected to M/D conversion at the timing of the sampling clock m, and pixel data r is continuously stored in the memory 119.

According to this method, in the case of RGB signals, the jitter between the horizontal synchronization signal S and the internal horizontal synchronization signal L is 1/12
fsc, that is, 1/4 pixel, and since the sampling clock m is completely synchronized with the internal horizontal synchronization signal l, the sampling jitter can be suppressed to 1/4 pixel. Further, in the case of an NTSG signal, since the phase of the reference clock j is synchronized with the burst signal, jitter of 1/8 pixel always occurs for each horizontal scanning line, but it is a sufficiently small value.

Effects of the Invention According to the present invention, it is possible to construct a sampling circuit with extremely low sampling jitter for both RGB signals and NTSC signals with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video signal reading device in an embodiment of the present invention, FIG. 2 is a timing diagram showing signal waveforms of each part thereof, and FIG. 3 is a block diagram of a video signal reading device in a first conventional example. FIG. 4 is a block diagram of a video signal reading device in a second conventional example. 101...NTSG signal input terminal, 1o2...
...Horizontal synchronization signal input terminal, 103...R
GB signal input terminal, 104...RGB signal detection means, 105...NTSC signal detection means, 10
6...Switching signal generating means, 107...
Input signal selection means, 108... Synchronization separation means,
109... Burst gate pulse generating means, 1
1o... Purst gate means, 111...
... Reference clock generation means, 112 ... Synchronization signal switching means, 113 ... Internal horizontal synchronization signal generation means, 114 ... 4 frequency division counter means, 115
...Reset signal generating means, 116...
・Address counter, 117...Load signal generation means, 118...M/D conversion means, 119.
...memory means. Name of agent: Patent attorney Toshio Nakao and one other person
Diagram 3 of 噌 ・1 listen ≦ OL

Claims (3)

[Claims] (1) Input video signal and horizontal synchronization signal, frequency f
Hz reference clock generation means and this reference clock
(N is an integer greater than or equal to 2) Frequency division counter means that divides the frequency and generates a sampling clock; A/D conversion means that A/D converts the input video signal at the timing of this sampling clock; and A/D conversion means that counts the sampling clock and generates a sampling clock. an address counter that generates an address; internal horizontal synchronization signal generation means that obtains a signal synchronized with fHz of a reference clock from a horizontal synchronization signal; and a signal that resets the frequency division counter means at the timing of the internal horizontal synchronization signal. A video signal reading device comprising: a reset signal generating means for generating a pixel address; and a load signal generating means for generating a signal for setting an initial value of a pixel address in the address counter from the internal horizontal synchronizing signal generating means. (2) Claim 1, wherein the reference clock has a frequency that is 2N, 3N, or 4N times (N = 2 or 4) the color subcarrier frequency of the NTSC signal, and the frequency division counter is an N frequency division counter. The video signal reading device described above. (3) an NTSC signal input terminal, an RGB signal input terminal, an NTSC signal detection means and/or an RGB signal detection means for detecting the presence or absence of an input signal, and either or both of the NTSC signal detection means and the RGB signal detection means. and input signal selection means for selecting the NTSG signal and the RGB signal based on the detection output of the reference clock generating means, when the NTSC signal is selected, the reference clock generating means generates the reference clock in phase synchronization with the burst signal of the NTSC signal. A video signal reading device according to claim 1 or 2, characterized in that: