JPH0793571B2 - Input waveform shaping circuit for PLL - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a PLL for multiplying and outputting the frequency of a reference signal.
The present invention relates to an input waveform shaping circuit of a (phase lock loop) circuit, and particularly to an input waveform shaping circuit for a PLL that generates a normal reference signal even when damping occurs.

[Prior Art] Conventionally, a PLL circuit that outputs a desired sampling clock according to the number of horizontal video pixels by accurately synchronizing the phase with, for example, a horizontal synchronization signal is well known. Generally, a waveform shaping circuit including a comparator is provided on the input side of this type of PLL circuit, and the horizontal synchronizing signal is input to the PLL circuit as a rectangular wave reference signal by the waveform shaping circuit.

FIG. 4 is a block diagram showing a conventional PLL input waveform shaping circuit. In the figure, (1) is an input terminal to which a horizontal synchronizing signal A having a frequency of, for example, several tens of kHz is applied, (2) is a comparator to which the horizontal synchronizing signal A is applied to a comparison input terminal (-), and (3) is a comparator. It is a variable voltage source for applying the threshold voltage B to the reference input terminal (+) of (2). The comparator (2) constitutes an input waveform shaping circuit for making the horizontal synchronizing signal A into a rectangular wave based on the threshold voltage B, and outputs the reference signal C having the same frequency as the horizontal synchronizing signal A. It has become.

(4) is a PLL that outputs a sampling clock D whose frequency is multiplied with respect to the reference signal C and whose phase is synchronized, and is composed of the following (41) to (44).

(41) is a programmable counter for setting the frequency of the sampling clock D to a desired value, and feeds back to the input side a set signal E which is (1 / N) times the frequency of the sampling clock D. (42) is a phase comparator (hereinafter referred to as PD) that detects the phase difference between the reference signal C and the set signal E and outputs a phase difference pulse F, (43)
Is a low-pass filter (hereinafter referred to as LPF) that outputs a voltage signal corresponding to the phase difference pulse F as a phase difference signal G, (4
4) is a desired frequency according to the phase difference signal G and a reference signal C
It is a voltage controlled oscillator (hereinafter referred to as VCO) that outputs a sampling lock D that is phase-locked with.

(5) is a program switch for setting the multiplication number N of the PLL (4) and is connected to the programmable counter (41). (6) is an output terminal from which the output signal of the PLL (4), that is, the sampling clock D is output.

Next, referring to the waveform diagrams of FIG. 5 and FIG.
The operation of the conventional PLL input waveform shaping circuit shown in the figure will be described.

First, in order to set the sampling clock D to a desired frequency, a programmable switch (5) sets a set value N, which is a multiplication number of the reference signal C, to a programmable counter (41).
Set to. Further, the threshold voltage B of the comparator (2) is properly set by the variable voltage source (3).

The horizontal synchronizing signal A applied to the input terminal (1) is compared with the threshold voltage B by the comparator (2) and becomes a rectangular wave reference signal C as shown in FIG.
Input to (42). Here, the reference signal C is shown to have a negative polarity.

On the other hand, the VCO (44) outputs the sampling clock D having a frequency corresponding to the phase difference signal G from the LPF (43), and the set signal E obtained by multiplying this frequency by 1 / N by the programmable counter (41) It is fed back to PD (42).

The PD (42) detects the phase difference between the reference signal C and the set signal E and outputs a phase difference pulse F. The phase difference pulse F is LP
The phase difference signal G is generated by F (43) and is input to the VCO (44). As a result, the VCO (44) outputs the sampling clock D having a frequency corresponding to the phase difference signal G and is fed back to the PD (42) via the programmable counter (41) again.

Thus, as shown in FIG. 5, the sampling clock D having a frequency N times that of the reference signal C and being phase-locked with the reference signal C is output from the output terminal (6).

At this time, if the frequency N of the horizontal synchronizing signal A is f _A and the dot clock frequency corresponding to the number of horizontal image pixels, that is, the frequency of the sampling clock D is f _D , the multiplication number N set by the program switch (5) is It is represented by N = f _D / f _A. Normally, when the number of horizontal video pixels is 1280, the multiplication number N is set to about 2000, and the frequency f _D of the sampling clock D output from the PLL (4) is about 100 MHz.

In reality, however, as shown in FIG. 6, the horizontal synchronizing signal A is disturbed due to damping or the like, and a pulse break C'is often generated in the reference signal C depending on the set value of the threshold voltage B. When the pulse crack C'occurs, the reference frequency of the PLL (4) is disturbed, so that the VCO (44)
Normal oscillation is impaired and a lock error occurs, and the desired sampling clock D cannot be obtained.

In order to prevent this lock error, the threshold voltage B that absorbs the fluctuation of the horizontal sync signal A must be set, but the fluctuation width of the horizontal sync signal A must be predicted before driving the PLL (4). It is difficult.

In addition, for example, as disclosed in Japanese Patent Laid-Open No. 60-251562, a data extraction circuit for optimizing a threshold level of a comparator to correct jitter and level fluctuations for the purpose of reproducing an input signal is also proposed. However, when a reflected signal occurs in the video signal transmission line, it is not possible to remove the erroneous signal due to the reflected signal to compensate the operation of the PLL. In other words, if the input signal at the input point of the PLL contains a reflected signal, it will be output as an erroneous signal if it is sampled internally, and the circuits after the PLL will operate as erroneous signals even if they are correct signals. become.

[Problems to be Solved by the Invention] As described above, in the conventional input waveform shaping circuit for PLL, the threshold voltage B of the comparator (2) is once set by the variable voltage source (3) to the PLL (4 ) Is fixed during operation, so if unpredictable waveform disturbance occurs in the horizontal sync signal A due to damping, etc., the reference signal C is disturbed and the PLL
There is a problem that (4) cannot operate normally.

The present invention has been made to solve the above problems, and a PLL capable of setting a threshold voltage capable of absorbing the waveform disturbance of the horizontal synchronizing signal as an input signal and always outputting a normal reference signal. The purpose is to obtain an input waveform shaping circuit for.

[Means for Solving Problems] An input waveform shaping circuit for a PLL according to the present invention is inserted on an input side of a PLL for multiplying and outputting a frequency of a reference signal, and an input signal for the PLL is set to a threshold voltage. In a PLL input waveform shaping circuit having a comparator for comparing and outputting a reference signal, a lock detection circuit for detecting the lock state of the PLL, and a threshold value based on the lock error signal output from this lock detection circuit. And a threshold value changing circuit for changing the voltage.

[Operation] In the present invention, the lock state of the PLL is always detected, and when the lock error occurs, the threshold voltage is automatically changed so as to remove the lock error.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 1 is a block diagram showing an embodiment of the present invention,
(1), (2), (4), (41) to (44), (5),
(6) and A to G are the same as described above.

(7) is a lock detection circuit that detects the locked state of the PD (42) including, for example, a comparator and a filter.
It is connected to the lock output terminal provided at (42).

(8) is a lock error signal from the lock detection circuit (7)
It is a threshold value changing circuit for changing the threshold voltage B according to LE, and is composed of the following (81) to (89).

(81) is a CPU, and (82) is a bus connected to the CPU.
(83) is a RAM for temporarily storing the data being processed by the CPU (81), (84) is a ROM storing the CPU (81) program and initial setting data, and (85) is a lock error. An input port to which the signal LE is input, (86) is an output port for outputting a calculation processing result of the CPU (81), and these are connected to the CPU (81) via the bus (82).

(87) is a DA converter that converts the signal value from the output port (86) into a current, and (88) is an IV converter that converts the output current of the DA converter (87) into a voltage signal and outputs the threshold voltage B. The operational amplifier (89) is a resistor inserted between the input and output of the operational amplifier (88).

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be described with reference to the flow chart of FIG. 2 and the waveform diagram of FIG.

First Step S1 First, a plurality of threshold values corresponding to the threshold voltage B to be changed are set and stored in the ROM (84). This threshold value may be set stepwise according to the magnitude of the lock error signal LE, or may be instantly switched to a predetermined value when the lock error signal LE is detected.

Second Step S2 Next, the PLL (4) is initially driven, and the lock detection circuit (7) detects the locked state of the PD (42), that is, the PLL (4). At this time, the initial setting value of the threshold voltage B is the same as the conventional one.

Third step S3 Then, it is determined whether or not the PLL (4) is locked,
If locked, the setting operation of the threshold voltage B is completed.

Fourth Step S4 On the other hand, as shown in FIG. 6, when the pulse break C'occurs and the lock detection circuit (7) outputs the lock error signal LE,
The CPU (81) recognizes that a lock error has occurred in the PLL (4) via the input port (85), and outputs the threshold data T stored in the ROM (84) via the output port (86). Is output and the current threshold voltage B is changed. That is, the threshold voltage B
Is set in an area outside the variation range of the horizontal synchronizing signal A shown by the diagonal lines in FIG. Although the threshold voltage B after the change is set above the shaded portion here, it may be set below the shaded portion.

Then, returning to the second step S2 and the third step S3 again, it is confirmed that the PLL (4) is normally locked, and the setting operation of the threshold voltage B is completed.

When the threshold voltage B is changed stepwise in the fourth step S4, the process returns to the second step S2 while changing the threshold data T by a predetermined width, and the steps S2 to S4 are repeated until the lock error signal LE is no longer output. You can repeat.

After setting the appropriate threshold voltage B in this way, the actual PLL
By driving (4), the waveform of the reference signal C is always maintained normal, and the PLL (4) can normally oscillate. Further, the lock error signal LE is not output from the lock detection circuit (7).

Further, since the lock detection circuit (7) always detects the locked state of the PLL (4) even during the operation of the PLL (4),
Even if the lock error signal LE is output, the threshold voltage B is corrected and the normal oscillation state can always be maintained.

That is, since the reference signal C whose waveform has been shaped by the comparator (2) is input to the PLL (4), for example, when a reflection signal or the like is mixed in the input signal A and the reference signal C includes an erroneous signal pulse. The lock error signal LE is always generated by this erroneous signal pulse. Therefore, the threshold value changing circuit (8)
Changes the threshold voltage B so as to remove the lock error signal LE so that the reference signal C from the comparator (2) does not include an erroneous signal pulse.

Although the lock detection circuit (7) is connected to the lock output terminal of the PD (42) in the above embodiment, it is connected to the output terminal of the PD (42) and the lock error signal LE is output based on the phase difference pulse F. You may do it.

Further, the case where the input signal applied to the input terminal (1) is the horizontal synchronizing signal A and the sampling clock D output from the output terminal (6) is a video signal has been described. It goes without saying that the same effect can be obtained even when applied to a PLL for signals.

[Effects of the Invention] As described above, according to the present invention, the reference signal is output by inserting it into the input side of the PLL for multiplying and outputting the frequency of the reference signal and comparing the input signal to the PLL with the threshold voltage. In a PLL input waveform shaping circuit having a comparator for locking, a lock detection circuit for detecting the lock state of the PLL, and a threshold for changing the threshold voltage based on the lock error signal output from this lock detection circuit. Since a change circuit is provided to automatically change the threshold voltage when a lock error occurs, it is possible to set a threshold voltage that can absorb the waveform disturbance of the input signal and always output a normal reference signal. There is an effect that a possible input waveform shaping circuit for PLL can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flow chart diagram for explaining the operation of the present invention.
FIG. 3 is a waveform diagram for explaining the threshold value changing operation according to the present invention, FIG. 4 is a block diagram showing a conventional PLL input waveform shaping circuit, and FIG. 5 is a diagram for explaining a general PLL operation. Waveform diagram, FIG. 6 is a waveform diagram for explaining pulse breakage by a conventional PLL input waveform shaping circuit. (2) …… Comparator, (4) …… PLL (7) …… Lock detection circuit, (8) …… Threshold change circuit (42) …… PD (Phase comparator) (81) …… CPU, (84 ) ... ROM A ... horizontal synchronizing signal (input signal) B ... threshold voltage, C ... reference signal LE ... lock error signal T ... threshold data In the drawings, the same reference numerals indicate the same or corresponding portions. .

Claims (3)

[Claims] 1. A PLL input having a comparator inserted into the input side of a PLL for multiplying the frequency of a reference signal and outputting the reference signal, and comparing the input signal to the PLL with a threshold voltage to output the reference signal. In the waveform shaping circuit, a lock detecting circuit for detecting the lock state of the PLL, and a threshold changing circuit for changing the threshold voltage based on a lock error signal output from the lock detecting circuit, An input waveform shaping circuit for PLL characterized by the following. 2. The input waveform shaping circuit for a PLL according to claim 1, wherein the lock detection circuit is connected to an output terminal or a lock output terminal of a PD included in the PLL. 3. A threshold value changing circuit is a ROM for storing data corresponding to a plurality of threshold values, and a threshold voltage applied to a comparator based on the threshold value data in the ROM when a lock error signal is detected. Claim 1 or 2 provided with the CPU for changing
Input waveform shaping circuit for PLL described in the paragraph.