JP2003037499A - Frequency synthesizer, connection method between reference signal oscillator and frequency synthesizer, and communication device employing them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency synthesizer that can decrease its output jitters, in a combination stage with a TCXO(temperature compensated crystal oscillator), when a gradient of a waveform of a reference oscillation input signal from the TCXO differs from an amplitude level, and to provide a connection method between the reference signal oscillator and the frequency synthesizer and a communication device employing them. SOLUTION: The frequency synthesizer is provided with a threshold level changing means that changes the threshold level, when it receives reference oscillation input signal from the TCXO. The threshold level change means employs a CMOS inverter circuit, comprising P-channel or N-channel field effect transistors connected in parallel or series, or whose gate length or gate width are differentiated or employs a comparator circuit or other configurations. Further, an input circuit is provided with a changeover circuit 42, comprising inverter circuits 34 to 36 having different threshold levels, and AND circuits 44 to 46 and installed at a pre-stage of a frequency divider 3 and control input terminals S1 to S3 permit selection of a threshold level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, a method for connecting a frequency synthesizer and a reference signal oscillator, and a communication apparatus using them, and more particularly to a frequency synthesizer used as a carrier wave oscillator or a local oscillator in a communication apparatus such as a mobile phone. And a method for connecting a frequency synthesizer and a reference signal oscillator.

[0002]

2. Description of the Related Art Digital modulation type mobile phones (hereinafter referred to as
In "PDC", the communication quality is basically determined by the bit error rate (hereinafter referred to as "BER") of the digital signal. The BER is determined by the digital modulation accuracy, which is measured by a vector error which is a position deviation of π / 4 shift QPSK (quadrature phase shift keying) from the constellation map which should originally be used in PDC. The modulation accuracy does not improve with a carrier whose signal phase is deteriorated, that is, with a lot of jitter. Therefore, in order to obtain a high performance communication device, an oscillator with little phase noise is required.

FIG. 17 is a block diagram showing the configuration of a conventional frequency synthesizer used for a carrier wave oscillator or a local oscillator of a communication device according to FIG. In the figure, 1 is a frequency synthesizer, a waveform shaping circuit 2 for inputting a reference oscillation input signal c from a reference signal oscillator 8 to shape the waveform, and a frequency divider 3 for dividing the output of the waveform shaping circuit 2. A voltage controlled oscillator (hereinafter referred to as “VCO”) 4 that generates a signal of a desired frequency, a frequency divider 5 that divides the output of the VCO 4, and an output of the frequency divider 3 and an output of the frequency divider 5. The phase comparator 6 for comparing the phases, and suppressing the high frequency component from the output of the phase comparator 6,
It is composed of a low-pass filter (hereinafter referred to as “LPF”) 7 that generates a control signal of the voltage controlled oscillator 4. As a result, the RF output signal f of the frequency synthesizer is a signal synchronized with the reference oscillation input signal c, and a signal having a frequency determined by the frequency division ratio of the frequency divider 3 and the frequency divider 5 is obtained.

[0004]

Since the conventional frequency synthesizer is configured as described above, if the reference oscillation input signal c has jitter, the jitter is propagated to the RF output signal f of the frequency synthesizer as it is. Therefore, a reference signal oscillator 8 having a small jitter such as a temperature compensated crystal oscillator (TCXO) is used (hereinafter, the reference signal oscillator is referred to as “TCXO”).

However, even if the TCXO 8 itself has no jitter, there is a problem in that the output signal thereof has a blunted waveform due to internal impedance, the load of the signal transmission path, etc., which causes jitter on the frequency synthesizer side.
Hereinafter, the phase synchronization by the phase comparator 6 will be described as being synchronized with the rising edge of the signal applied to the frequency divider 3.

For example, when the TCXO 8 has a capacitive load, the reference oscillation input signal c has a waveform as shown in FIG. 18 (a). The reference oscillation input signal c is binarized by the input threshold level of the waveform shaping circuit 2 by passing through the waveform shaping circuit 2 and input to the frequency divider 3.
Here, assuming that the input threshold levels of the waveform shaping circuit 2 are A, B, and C, the signals after waveform shaping become the waveforms of (b), (c), and (d) of FIG. Therefore, when the input threshold level is A, the rising slope of the reference oscillation input signal is gentle, so that if there is an amplitude fluctuation or the like, the phase fluctuation of the rising after waveform shaping becomes large and the RF output signal f becomes large. Jitter occurs. On the other hand, when the input threshold level is C, the slope of the reference oscillation input signal is steep, so that the phase fluctuation of the rising edge is small and the jitter of the RF output signal f is small even if there is an amplitude variation. When the input threshold level is B, it is in the middle.

On the other hand, when the TCXO 8 has an inductive load, the reference oscillation input signal c has a waveform as shown in FIG. 19 (a). Here, assuming that the input threshold levels of the waveform shaping circuit 2 are A, B, and C, the signals after waveform shaping become the waveforms of (b), (c), and (d) of FIG. Therefore, when the input threshold level is A, the slope of the reference oscillation input signal is steep, so that the phase fluctuation is small when there is an amplitude fluctuation and the like, and the jitter of the RF output signal f is also small. On the other hand, when the input threshold level is C, the inclination of the reference oscillation input signal is gentle, so that the phase fluctuation is large when there is an amplitude fluctuation and the like, and a large jitter is generated in the RF output signal f. When the input threshold level is B, it is in the middle.

As described above, in the conventional frequency synthesizer, the input threshold level is not always in a desirable relationship with the reference oscillation input signal waveform, and there is a problem that a large jitter may occur in the RF output signal. It was

Therefore, the main object of the present invention is to
When the reference oscillation input signal from the CXO has a different waveform slope depending on the amplitude, it is possible to reduce the output jitter of the frequency synthesizer in the combination stage with the TCXO, the frequency synthesizer, the frequency synthesizer, and the TCXO.
And a communication device using them.

[0010]

A frequency synthesizer according to the present invention includes an input circuit for inputting a reference oscillation input signal from a TCXO to generate a signal for phase comparison, a VCO for generating a signal of a desired frequency, and a VCO. Frequency divider that divides the output of the input circuit, a phase comparison circuit that compares the phases of the output of the input circuit and the output of the frequency divider, and a high-frequency component is suppressed from the output of the phase comparator to generate a VCO control signal. In a frequency synthesizer having a low-pass filter and generating a signal of a desired frequency in synchronization with a signal from the TCXO, a threshold level changing means for changing a threshold level when inputting a reference oscillation input signal is provided.

Further, the frequency synthesizer of the present invention is
The threshold level changing means may complementarily connect the P-channel field effect transistor and the N-channel field effect transistor to the power supply and the ground, and may include an inverter circuit in which one field effect transistor is connected in parallel. . When a plurality of P-channel field effect transistors are connected in parallel, the threshold level of the inverter circuit becomes high, and when a plurality of N-channel field effect transistors are connected in parallel, the threshold level of the inverter circuit becomes low. This makes it easy to construct frequency synthesizers with different input threshold levels, so that the TCX
In the combination stage with O, the output jitter can be reduced by selecting the frequency synthesizer having the optimum input threshold level according to the reference oscillation input signal waveform from the TCXO.

Further, the frequency synthesizer of the present invention is
The threshold level changing means may complementarily connect the P-channel field effect transistor and the N-channel field effect transistor to the power supply and the ground, and may include an inverter circuit in which one field effect transistor is connected in series. . When a plurality of P-channel field effect transistors are connected in series, the threshold level of the inverter circuit becomes low, and when a plurality of N-channel field effect transistors are connected in series, the threshold level of the inverter circuit becomes high. This makes it easy to construct frequency synthesizers with different input threshold levels, so that the TCX
In the combination stage with O, the output jitter can be reduced by selecting the frequency synthesizer having the optimum input threshold level according to the reference oscillation input signal waveform from the TCXO.

Further, the frequency synthesizer of the present invention is
The threshold level changing means connects the P-channel field effect transistor and the N-channel field effect transistor complementarily to the power source and the ground, and the gate length of one field effect transistor and the gate length of the other field effect transistor. It may include an inverter circuit having a difference. If the gate length of the P-channel field effect transistor is shortened with respect to the gate length of the N-channel field effect transistor, the threshold level of the inverter circuit becomes high, and the gate length of the P-channel field effect transistor becomes larger than that of the N-channel field effect transistor. Longer, the threshold level of the inverter circuit becomes lower. As a result, a frequency synthesizer having different input threshold levels can be easily configured. Therefore, at the stage of combination with the TCXO, an output can be obtained by selecting a frequency synthesizer having an optimum input threshold level according to the reference oscillation input signal waveform from the TCXO. Jitter can be reduced.

Further, the frequency synthesizer of the present invention is
The threshold level changing means connects the P-channel field effect transistor and the N-channel field effect transistor complementarily to the power source and the ground, and the gate width of one field effect transistor and the gate width of the other field effect transistor. It may include an inverter circuit having a difference. If the gate width of the P-channel field effect transistor is widened with respect to the gate width of the N-channel field effect transistor, the threshold level of the inverter circuit becomes high, and the gate width of the P-channel field effect transistor becomes larger than that of the N-channel field effect transistor. If it is made narrower, the threshold level of the inverter circuit becomes lower. As a result, a frequency synthesizer having different input threshold levels can be easily configured. Therefore, at the stage of combination with the TCXO, an output can be obtained by selecting a frequency synthesizer having an optimum input threshold level according to the reference oscillation input signal waveform from the TCXO. Jitter can be reduced.

Further, the frequency synthesizer of the present invention is
The threshold level changing means may include a comparison circuit for comparing the reference oscillation input signal with the reference voltage. As a result, a frequency synthesizer having different input threshold levels can be easily configured. Therefore, at the stage of combination with the TCXO, an output can be obtained by selecting a frequency synthesizer having an optimum input threshold level according to the reference oscillation input signal waveform from the TCXO. Jitter can be reduced.

Further, the frequency synthesizer of the present invention is
The threshold level changing means may include a reference voltage input terminal, and the voltage at the reference voltage input terminal may be used as the reference voltage. Thus, by setting the voltage of the reference voltage input terminal after the combination with TCXO, the input threshold level with which the output jitter becomes small can be easily selected.

Further, the frequency synthesizer of the present invention is
The input circuit may include a plurality of inverter circuits having different threshold levels. This makes it possible to easily select the input threshold level at which the output jitter becomes small in the combination stage with the TCXO.

Further, the frequency synthesizer of the present invention is
The input circuit may include a control input terminal, and may include switching means for switching which of a plurality of inverter circuits having different threshold levels is to be used according to the logic level of the control input terminal. Thus, by setting the logic level of the control input terminal after the combination with TCXO, the input threshold level with which the output jitter becomes small can be easily selected.

Further, the frequency synthesizer of the present invention is
A serial-parallel conversion circuit and serial data input terminal are further provided for setting the frequency division ratio of the frequency divider, and the frequency division ratio of the frequency divider is set by the signal from the serial data input terminal to generate a signal of the desired frequency. The frequency synthesizer may be configured to include a switching unit that switches which of the plurality of inverter circuits having different threshold levels is used by the input circuit according to the input data from the serial data input terminal. This makes it possible to easily select the input threshold level with which the output jitter is reduced by using the data input to the serial data input terminal after the combination with TCXO.

Frequency Synthesizer and TCXO of the Present Invention
The connection method of 1 has a method of providing a potential difference between the ground potential of the input circuit of the frequency synthesizer and the ground potential of the output circuit of the TCXO. By providing a potential difference to the ground potential, the input threshold level of the frequency synthesizer can be easily changed at the stage of combination with the TCXO, and the output jitter of the frequency synthesizer can be reduced by selecting the optimum input threshold.

The frequency synthesizer of the present invention and the T
The method of connecting the CXO may have a method of providing a potential difference between the power supply potential of the input circuit of the frequency synthesizer and the power supply potential of the output circuit of the TCXO. By providing a potential difference in the power supply potential, the input threshold level of the frequency synthesizer can be easily changed when combined with the TCXO, and the output jitter of the frequency synthesizer can be reduced by selecting the optimum input threshold.

The frequency synthesizer of the present invention and the T
The CXO may be connected by using a constant voltage element as the method of providing a potential difference. By using the constant voltage element, the potential difference between the frequency synthesizer and the TCXO can be provided simply and stably.

The communication device of the present invention uses the frequency synthesizer of the present invention.

The communication device of the present invention may use the method of connecting the frequency synthesizer and the TCXO of the present invention.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments of the invention with reference to the drawings.

[0026]

1 is a circuit diagram of an input section of a first embodiment of a frequency synthesizer of the present invention. In the figure, 10 is a frequency synthesizer, which shows only the input circuit portion for shaping the waveform of the reference oscillation input signal c. As shown, a P-channel field effect transistor (hereinafter referred to as "PMOS") and an N-channel field effect transistor (hereinafter referred to as "NMOS") as an input circuit.
An inverter circuit using a complementary field effect transistor (hereinafter referred to as “CMOS”) in which is connected to a power source and ground in a complementary manner is used, and a reference oscillation input signal c is applied via a resistor. The parts other than the waveform shaping circuit are the same as those of the conventional frequency synthesizer of FIG. 17, and the output signal of this inverter circuit is added to the frequency divider 3.

Here, in this embodiment, P of the inverter circuit is used.
Two MOSs are connected in parallel. Thus, the PMOS
The parallel conductance (hereinafter referred to as “g
m ”), and a large drain current flows with a smaller gate-source voltage. Here, since the PMOS and NMOS connected in parallel are connected in series, the drain currents are equal. Even if gm of PMOS increases, drain current is limited by NMOS, so PM connected in parallel
OS requires less gate-source voltage, and the input threshold level shifts to the Vcc side.

Therefore, the reference oscillation input signal c is shown in FIG.
When the waveform has a large slope at a large amplitude as shown in (a), it is possible to reduce the phase fluctuation of the falling edge of the signal applied to the frequency divider 3 by using the frequency synthesizer 10. When the phase synchronization by the frequency divider 6 is synchronized with the falling edge of the signal applied to the frequency divider 3, the output jitter can be reduced.

FIG. 2 is a circuit diagram of the input section of the second embodiment of the frequency synthesizer of the present invention. In the figure, 12 is a frequency synthesizer, and similarly, a reference oscillation input signal c
It shows only the input circuit part that performs the waveform shaping of. In this embodiment, two NMOSs of the inverter circuit are connected in series. In this way, by connecting NMOSs in series, the transconductance gm decreases, and a larger gate-source voltage is required to pass the same drain current, so the input threshold level shifts to the Vcc side.

Therefore, as in the case of the first embodiment, when the reference oscillation input signal c has a large waveform slope at a large amplitude as shown in FIG. 19A, the frequency synthesizer 12 is used. Since the phase fluctuation of the trailing edge of the signal applied to the frequency divider 3 can be reduced, the output jitter is reduced when the phase synchronization by the phase comparator 6 is synchronized with the trailing edge of the signal applied to the frequency divider 3. Can be made smaller.

FIG. 3 is a circuit diagram of the input section of the third embodiment of the frequency synthesizer of the present invention. In the figure, 14 is a frequency synthesizer, and similarly, a reference oscillation input signal c
It shows only the input circuit part that performs the waveform shaping of. In this embodiment, two PMOSs of the inverter circuit are connected in series. In this way, by connecting the PMOSs in series, the transconductance gm is reduced, and a larger gate-source voltage is required to pass the same drain current, so that the input threshold level is shifted to the ground side.

Therefore, the reference oscillation input signal c is, for example, as shown in FIG.
8 (a), when the waveform has a large slope at a small amplitude, the use of the frequency synthesizer 14 can reduce the phase fluctuation at the falling edge of the signal applied to the frequency divider 3. When the phase synchronization by the comparator 6 is synchronized with the falling edge of the signal applied to the frequency divider 3, the output jitter can be reduced.

FIG. 4 is a circuit diagram of the input section of the fourth embodiment of the frequency synthesizer of the present invention. In the figure, 16 is a frequency synthesizer, and similarly, a reference oscillation input signal c
It shows only the input circuit part that performs the waveform shaping of. In this embodiment, two NMOSs of the inverter circuit are connected in parallel. Thus, by connecting the NMOSs in parallel, the transconductance gm increases, and a smaller gate-source voltage is required for the same drain current.
The input threshold level shifts to the ground side.

Therefore, the reference oscillation input signal c is, for example, as shown in FIG.
8 (a), when the waveform has a large slope at a small amplitude, the use of the frequency synthesizer 16 can reduce the phase fluctuation of the falling edge of the signal applied to the frequency divider 3. When the phase synchronization by the comparator 6 is synchronized with the falling edge of the signal applied to the frequency divider 3, the output jitter can be reduced.

In the above embodiment, the PMOS or NMOS is used.
Although two of the above are connected in parallel or two are connected in series, the present invention is not limited to this, and three or more may be connected in parallel or three or more may be connected in series. It goes without saying that it is good. This allows
Further, the input threshold level can be changed greatly.

As described above, by connecting the input part of the frequency synthesizer to the PMOS and the NMOS complementarily to the power supply and the ground, and connecting one or more of the PMOS and the NMOS in parallel or in series, the input threshold level is increased. , The output jitter can be reduced by selecting the frequency synthesizer having the optimum input threshold level according to the reference oscillation input signal waveform from the TCXO in the combination stage with the TCXO.

In the above-described embodiment, the input threshold level is changed by decreasing or increasing gm of one by changing the input threshold level by connecting a plurality of PMOS and NMOS in parallel or by connecting a plurality of them in series. The input threshold level can be changed by providing a difference in gate length. That is, when the gate length is shortened, gm increases, and when the gate length is lengthened, gm decreases. Therefore, when the gate length of the PMOS is shortened with respect to the gate length of the NMOS, the input threshold level increases and Pm increases.
If the gate length of the MOS is made longer than the gate length of the NMOS, the input threshold level becomes low.

As described above, the input parts of the frequency synthesizer are connected to the PMOS and NMOS in a complementary manner with respect to the power supply and the ground, and the gate lengths of one side and the gate length of the other side are made different from each other, whereby the input threshold levels are different. Since the frequency synthesizer can be easily constructed, the output jitter can be reduced by selecting the frequency synthesizer having the optimum input threshold level according to the reference oscillation input signal waveform from the TCXO in the combination stage with the TCXO.

Similarly, the input threshold level can be changed by providing a difference between the gate widths of the PMOS and the NMOS. That is, when the gate width is widened, gm increases, and when the gate width is narrowed, gm decreases. Therefore, when the PMOS gate width is wider than the NMOS gate width, the input threshold level becomes high and the PMOS gate width becomes large. When the gate width of the NMOS is narrowed, the input threshold level becomes low.

As described above, by connecting the input portion of the frequency synthesizer to the PMOS and the NMOS complementarily to the power source and the ground and providing a difference in the gate width of one side and the gate width of the other side, the input threshold levels are different. Since the frequency synthesizer can be easily constructed, the output jitter can be reduced by selecting the frequency synthesizer having the optimum input threshold level according to the reference oscillation input signal waveform from the TCXO in the combination stage with the TCXO.

In the above embodiment, the phase synchronization by the phase comparator 6 was described as being synchronized with the falling edge of the signal applied to the frequency divider 3. This is because the input part of the frequency synthesizer uses PMOS and NMOS as power supplies. This is because the inverter circuit is configured to be connected complementarily to the ground, and the inverted output is input to the frequency divider 3. Therefore, the inverter circuit is connected in series to the even number stage and the non-inverted output is input to the frequency divider 3. By doing so, the output jitter is reduced when the phase synchronization by the phase comparator 6 is synchronized with the rising edge of the signal applied to the frequency divider 3. These are for convenience of description, and in any case, the output jitter can be reduced by selecting the optimum input threshold level according to the reference oscillation input signal waveform from the TCXO.

FIG. 5 is a circuit diagram of the input section of the fifth embodiment of the frequency synthesizer of the present invention. In the figure, reference numeral 18 is a frequency synthesizer, and similarly, a reference oscillation input signal c
It shows only the input circuit part that performs the waveform shaping of. In the present embodiment, the waveform shaping is performed by using the comparison circuit CMP as the input circuit. The inverting input of the comparator circuit CMP is connected to the reference oscillation input terminal, and the non-inverting input of the comparator circuit CMP is connected to Vcc via the resistor R1 and ground via the resistor R2. Therefore, the reference oscillation input signal c is compared with the reference voltage Vref obtained by dividing Vcc by the resistors R1 and R2, and the inversion signal binarized with the reference voltage Vref as the input threshold level is supplied to the frequency divider 3. It In this way, the waveform shaping circuit having an arbitrary input threshold level can be easily configured by the comparison circuit.

In the above embodiment, the reference voltage is described as the voltage division of the resistors R1 and R2. However, the present invention is not limited to this, and a large number of resistors may be provided for selective use. A variable resistor may be used. This makes it possible to select the optimum input threshold level according to the reference oscillation input signal waveform after combination with TCXO.

FIG. 6 is a circuit diagram of the input section of the sixth embodiment of the frequency synthesizer of the present invention. In the figure, reference numeral 20 is a frequency synthesizer for shaping the waveform of the reference oscillation input signal c by the comparison circuit CMP as in the fifth embodiment. In this embodiment, the non-inverting input of the comparison circuit CMP is connected to the reference voltage generated by the resistor R1 and the constant voltage diode ZD. Therefore, in the present embodiment, a waveform shaping circuit that sets the breakdown voltage V _ZD of the constant voltage diode to the input threshold level is configured. As described above, by generating the reference voltage using the constant voltage diode, the input threshold level of the waveform shaping circuit is stabilized.

FIG. 7 is a circuit diagram of the input section of the seventh embodiment of the frequency synthesizer of the present invention. In the figure, reference numeral 22 is a frequency synthesizer, which shapes the waveform of the reference oscillation input signal c by the comparison circuit CMP as in the fifth embodiment. In this embodiment, the reference voltage input terminal Vth is provided, and the non-inverting input of the comparison circuit CMP is connected to the reference voltage input terminal Vth. Therefore, in the present embodiment, a waveform shaping circuit that sets the reference voltage Vref applied to the reference voltage input terminal Vth as the input threshold level is configured. As described above, since the threshold level when the reference oscillation signal is input can be set to an arbitrary voltage from the outside, the TCXO
In the case where the input signal from the input signal has a different waveform slope depending on the amplitude level, it is possible to reduce the output jitter of the frequency synthesizer after the combination with the TCXO.

The comparator circuits used in the fifth to seventh embodiments use operational amplifiers, and the positive power source (Vdd) is Vcc.
By connecting the negative power source (Vee) to the ground,
Easy to configure. If a negative voltage can be supplied as the reference voltage, an adder circuit using an operational amplifier may be used as the comparison circuit to add the reference oscillation input signal and the reference voltage.

Further, since the comparison circuit used in the fifth to seventh embodiments applies the reference oscillation input signal to the inverting input and the reference voltage to the non-inverting input, it is an inverting type waveform shaping circuit. Although the reference oscillation input signal is applied to the non-inverting input and the reference voltage is applied to the inverting input, a non-inverting waveform shaping circuit may be used, and the same effect is obtained.

Next, a frequency synthesizer including a plurality of inverter circuits having different input threshold levels as described above will be described. FIG. 8 is a block configuration diagram of an eighth embodiment of the frequency synthesizer of the present invention. In the figure, 30 is a frequency synthesizer, and three inverter circuits 34, 3 with different input threshold levels are provided.
A waveform shaping circuit 32 composed of 6 and 38 is provided. The inverter circuit 34 is an inverter circuit having a high input threshold level, and, for example, one in which PMOSs are connected in parallel as shown in FIG. 9A is used. The inverter circuit 36 is an inverter circuit having an intermediate input threshold level.
As shown in (b), a single complementary connection of PMOS and NMOS is used. The inverter circuit 38 is an inverter circuit having a low input threshold level, and for example, an NMOS circuit in which NMOSs are connected in parallel as shown in FIG. 9C is used.

The inputs of the inverter circuits 34, 36 and 38 are connected to the reference oscillation input terminals A, B and C, respectively, and the outputs of the inverter circuits 34, 36 and 38 are wired ORed and connected to the input of the frequency divider 3. ing.

Therefore, when the output of the TCXO8 is connected to the reference input terminal A, the input threshold level is high,
In the case where the reference oscillation input signal c has a large waveform slope at a place where the amplitude is large as shown in FIG. 19A, the phase fluctuation at the falling edge of the signal applied to the frequency divider 3 can be reduced, so that the phase comparison is performed. When the phase synchronization by the frequency divider 6 is synchronized with the falling edge of the signal applied to the frequency divider 3, the output jitter can be reduced.

Further, the output of TCXO8 is connected to the reference input terminal C.
Since the input threshold level is low, the reference oscillation input signal c has a high slope of the waveform at a small amplitude portion as shown in FIG. 18A, for example. Since the downward phase fluctuation can be reduced, the output jitter can be reduced when the phase synchronization by the phase comparator 6 is synchronized with the falling edge of the signal applied to the frequency divider 3.

Therefore, in the frequency synthesizer of this embodiment, the optimum input corresponding to the signal waveform of the reference oscillation input signal c is selected depending on which of the reference oscillation input terminals A, B and C is connected in the combination stage with the TCXO 8. Threshold level can be selected to reduce output jitter.

In the above embodiment, the inverter circuits 34-3 are used.
Although the output of 8 is described as wired OR for simplicity, in this case, the reference oscillation input terminal to which the TCXO 8 is not connected needs to be processed so that the reference oscillation input signal c is transmitted to the frequency divider 3. is there. For example, Wired OR
Is not used when is positive logic, the reference oscillation input pin is logic H
Set to. The inverter circuit is wired OR
Needless to say, if it is not suitable for connection, an OR circuit that takes the logical OR of the outputs of the inverter circuits may be provided.

FIG. 10 is a block diagram of the ninth embodiment of the frequency synthesizer of the present invention. In the figure, 40
Is a frequency synthesizer, and control input terminals S1, S
2 and S3, and instead of the waveform shaping circuit 32 of the eighth embodiment, a switching circuit 42 including three inverter circuits 34, 36, 38 and AND circuits 44, 46, 48 having different input threshold levels was used. It is a thing.

The inverter circuits 34, 36 and 38 are the same as those in the eighth embodiment, their inputs are commonly connected to the reference oscillation input terminal, and the outputs of the inverter circuits 34, 36 and 38 are AND circuits 44 and 36, respectively. It is connected to one input of 46 and 48. Further, AND circuits 44, 46, 4
The other inputs of 8 are control input terminals S1, S2, S, respectively.
3 and the outputs of the AND circuits 44, 46 and 48 are wired-ORed and connected to the input of the frequency divider 3.

Therefore, by setting any one of the control input terminals S1, S2 and S3 to logic H and the other to logic L, AN
One of the D circuits 44, 46, and 48 is selected, and the A
The input threshold level of the inverter circuit connected to the ND circuit is selected. Thus, by setting the logic level of the control input terminal after the combination with the TCXO8, the optimum input threshold level according to the signal waveform of the reference oscillation input signal c can be selected, and the output jitter can be reduced.

In the above embodiment, the outputs of the AND circuits 34 to 38 are described as wired OR for the sake of simplicity, but it goes without saying that an OR circuit which takes a logical OR of three inputs may be used.

In the above embodiment, the control input terminal S1
S3 are provided, but the terminals are not provided, the changeover switch is provided inside the frequency synthesizer, and the inputs of the AND circuits 34 to 38 to be selected are set to logic H, and the unselected AND circuit 34 is provided.
The inputs to 38 may be set to logic L.

FIG. 11 is a block diagram of the tenth embodiment of the frequency synthesizer of the present invention. The frequency synthesizer 50 of the present embodiment has a serial / parallel conversion setting device 52 for setting a frequency division ratio in the frequency dividers 3 and 5, and a serial data input terminal for setting data in the serial / parallel conversion setting device 52. , A clock input terminal and a strobe input terminal.
The frequency division ratio is set by converting the serial data into the serial data input terminal, the clock signal for synchronizing the serial data into the clock input terminal, and converting the transmitted serial data into parallel data. The strobe signal set in the memory for setting the division ratio of 5 is input to the strobe input terminal. As a result, the frequency synthesizer 50 can obtain the RF output signal f having the frequency determined by the frequency division ratio of the frequency divider 3 and the frequency divider 5 set by the external serial data with respect to the reference oscillation input signal c.

In this embodiment, the switching circuit 42 of the ninth embodiment is used.
In, 3 bits of the serial data are used as control inputs. Therefore, if there is an unused bit in the memory for setting the division ratio of the frequency divider 3 or the frequency divider 5, this is utilized, and the unused bit output of that memory is switched to the switching circuit 42.
If there is no unused bit, a separate control memory is provided, 3 bits of serial data is added and the strobe signal is used to set the control memory, and the output of that memory is input to the switching circuit 42. May be

As described above, if a part of the serial data for setting the division ratio is used as the control input signal of the switching circuit 42, which input threshold level is used without providing a special control input terminal. Can be selected. This makes it possible to select the optimum input threshold level according to the signal waveform of the reference oscillation input signal c by using the data input to the serial data input terminal after the combination with the TCXO 8 and reduce the output jitter.

In the above embodiment, the frequency synthesizer has been described as having the frequency divider 3 for dividing the reference oscillation input, but the reference oscillation input is not divided and the direct phase comparison circuit 6 is used.
It goes without saying that the phase comparison may be performed with.

In the eighth to tenth embodiments, an input circuit having different input threshold levels is shown in FIG.
Although the inverter circuits of (c) to (c) are used, the present invention is not limited to this, and any input circuit having different input threshold levels may be used, including the inverter circuits of the first to seventh embodiments. It may be one. Further, in the eighth to tenth embodiments, the three-stage inverter circuit having the high, medium, and low input threshold levels is provided, but the present invention is not limited to this, and different input threshold levels may be set. The same effect can be obtained as long as it has two or more inverter circuits.

Next, a method for changing the input threshold level of the frequency synthesizer by changing the connection method between the frequency synthesizer and the TCXO will be described. FIG. 12 shows the frequency synthesizer and TCXO of the present invention.
It is a connection diagram of a first embodiment of a connection method with. In the figure, the frequency synthesizer 1 and the TCXO 8 are the same as the conventional ones, and the output signal terminal OUT of the TCXO 8 is connected to the input signal terminal IN of the frequency synthesizer 1. In this embodiment, the GND potential of the frequency synthesizer 1 is set to the resistance R
1 and a constant voltage diode ZD1 are used to apply a bias. As a result, the GND potential of the frequency synthesizer 1 is raised by the breakdown voltage V _ZD1 of the constant voltage diode ZD1, and the input threshold level of the frequency synthesizer 1 is relatively increased by about V _ZD1 / 2.

FIG. 13 shows a frequency synthesizer of the present invention.
It is a connection diagram of a second embodiment of the connection method with the TCXO. Figure
, The frequency synthesizer 1 and TCXO8 are
The output signal terminal OUT of the TCXO8 is the same.
Connected to the input signal terminal IN of the frequency synthesizer 1.
It In this embodiment, the GND potential on the TCXO8 side is set to the resistance R
2 and bias by the constant voltage diode ZD2
It was done like this. As a result, the GN of TCXO1
The D potential is the breakdown voltage V of the constant voltage diode ZD2. _ZD2Only
Lifting, frequency synthesizer 1 input threshold
Level is about V_ZD2/ 2 lower.

As shown in the first and second embodiments of the method of connecting the frequency synthesizer and the TCXO, by providing a potential difference between the ground potential of the input circuit of the frequency synthesizer and the output circuit of the TCXO, the frequency synthesizer is provided. You can change the input threshold level of the TCXO
In the case where the waveform of the input signal from (1) has a different waveform slope depending on the amplitude, it is possible to reduce the output jitter of the frequency synthesizer by selecting the optimum input threshold in the combination stage with TCXO.

FIG. 14 is a connection diagram of the third embodiment of the connection method between the frequency synthesizer and the TCXO of the present invention. In this embodiment, the frequency synthesizer 1 and the TCXO8 are the same as those of the conventional one, but the Vcc potential on the frequency synthesizer 1 side is biased by the resistor R3 and the constant voltage diode ZD3. As a result, the Vcc potential of the frequency synthesizer 1 is lowered by the breakdown voltage V _ZD3 of the constant voltage diode ZD3, and the input threshold level of the frequency synthesizer 1 is relatively approximately V.
_It becomes lower by _ZD3 / 2.

FIG. 15 shows a frequency synthesizer of the present invention.
It is a connection diagram of 4th Example of the connection method with TCXO. Figure
, 1 is a frequency synthesizer and 8 is a TCX
It is O. In this embodiment, the frequency synthesizer 1 and TC
XO8 is the same as the conventional one, but TCXO8 side
Vcc potential of the resistor R4 and constant voltage diode ZD4
This is to give a bias. By this
Therefore, the Vcc potential of TCXO8 is the constant voltage diode ZD4.
Breakdown voltage V _ZD4Frequency synthesizer
Input threshold level of 1 is about V_ZD4/ 2
Get higher.

As shown in the third and fourth embodiments of the connection method between the frequency synthesizer and the TCXO, by providing a potential difference between the power supply potentials of the input circuit of the frequency synthesizer and the output circuit of the TCXO, the frequency synthesizer is provided. You can change the input threshold level of the TCXO
In the case where the waveform of the input signal from (1) has a different waveform slope depending on the amplitude, it is possible to reduce the output jitter of the frequency synthesizer by selecting the optimum input threshold in the combination stage with TCXO.

In the first to fourth embodiments of the method of connecting the frequency synthesizer and the TCXO, the constant voltage diode is used as a method of providing a potential difference between the ground potential and the power supply potential, but the method is not limited to this. Instead, it may be one that uses the forward voltage of the diode or one that uses a separately prepared constant voltage power supply.

In the first to fourth embodiments of the method of connecting the frequency synthesizer and the TCXO, the method of providing a potential difference in the ground potential or the power supply potential is explained as biasing the GND or Vcc of the frequency synthesizer or TCXO. However, it is not limited to this,
It is also possible to provide a GND terminal or a Vcc terminal only for the input circuit of the frequency synthesizer or only the output circuit of the TCXO and to apply a bias only to that portion. As a result, the input threshold level of the frequency synthesizer can be changed without affecting the operation of the frequency synthesizer itself or the TCXO itself.

Next, a description will be given of the case where the frequency synthesizer of the present invention or the method of connecting the frequency synthesizer and the TCXO of the present invention is used in a mobile phone. FIG. 16 is a block configuration diagram according to an embodiment of the communication device of the present invention. In the figure, the signal received from the antenna is amplified by the amplifier AMPb via the duplexer DPX, and then only the signal in the required band is extracted by the bandpass filter BPFb and mixed with the signal from the frequency synthesizer 60 by the mixer MIXb. It An intermediate frequency band of the mixed signal is taken out by an intermediate frequency filter IF, amplified by an amplifier AMPc, a reception signal is demodulated by a demodulator, and sent to a multiplexing control circuit.

On the other hand, the transmission signal generated by the multiplexing control circuit is modulated by the modulator and mixed with the signal from the frequency synthesizer 60 by the mixer MIXa. Of the mixed signal, only the signal in the high frequency band is extracted by the bandpass filter BPFa, amplified by the amplifier AMPa, and sent to the antenna via the duplexer DPX.

The audio codec encodes the signal from the microphone and sends it to the multiplexing control circuit, converts the demodulated signal from the multiplexing control circuit into an audio signal, and gives it to the speaker. The CPU controls the multiplexing control circuit, reads the state of the key switch, outputs a display signal to the display, and gives a drive signal to the vibrator.

Frequency synthesizer 60 used here
Generates a signal of a frequency necessary for frequency conversion based on the reference oscillation input from the TCXO 62, but a high performance mobile phone requires a stable signal with little phase noise. However, depending on the signal waveform of the TCXO 62 used, the phase noise may increase at the normal input threshold of the frequency synthesizer 60.

Therefore, in the communication device of the present invention, the frequency synthesizer of the present invention is used as the frequency synthesizer to be used, and the input threshold level is changed in accordance with the inclination of the signal waveform of the TCXO62 in the manufacturing stage, thereby selecting the frequency synthesizer. It is possible to reduce the jitter and obtain a highly reliable communication device.

The frequency synthesizer of the present invention and the T
By using the CXO connection method, the jitter can be reduced by selecting the connection method in which the input threshold level is changed according to the slope of the signal waveform of the TCXO 62 in the manufacturing stage.

In the above embodiment, the case where the frequency synthesizer of the present invention is used for the local oscillator of a mobile phone has been described, but the present invention is not limited to this and may be used for a carrier oscillator. Has the same effect.

In the above embodiment, the case where the frequency synthesizer of the present invention is used in a mobile phone has been described, but the present invention is not limited to this.
Any communication device may be used as long as the frequency synthesizer is combined with the TCXO at the manufacturing stage, and similar effects can be obtained.

[0080]

The frequency synthesizer of the present invention has a TC
Since the threshold level changing means for changing the threshold level at the time of inputting the reference oscillation input signal from the XO is included, when the reference oscillation input signal from the TCXO has a different waveform slope depending on the amplitude, the frequency is increased in combination with the TCXO. The output jitter of the synthesizer can be reduced.

Frequency Synthesizer and TCXO of the Present Invention
The connection method can change the threshold level when the frequency synthesizer inputs the reference oscillation signal from the TCXO, so when the input signal from the TCXO has a different waveform slope depending on the amplitude, it can be combined with the TCXO. In, there is an effect that the output jitter of the frequency synthesizer can be reduced.

Since the communication device of the present invention uses the frequency synthesizer of the present invention or uses the method of connecting the frequency synthesizer and the TCXO of the present invention, the TCXO
When the waveform of the input signal from the device has a different waveform slope depending on the amplitude, it is possible to reduce the jitter at the manufacturing stage of the communication device and to construct a highly reliable communication device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an input section of a first embodiment of a frequency synthesizer of the present invention.

FIG. 2 is a circuit diagram of an input section of a second embodiment of the frequency synthesizer of the present invention.

FIG. 3 is a circuit diagram of an input section of a third embodiment of the frequency synthesizer of the present invention.

FIG. 4 is a circuit diagram of an input section of a fourth embodiment of the frequency synthesizer of the present invention.

FIG. 5 is a circuit diagram of an input unit of a fifth embodiment of the frequency synthesizer of the present invention.

FIG. 6 is a circuit diagram of an input section of a sixth embodiment of the frequency synthesizer of the present invention.

FIG. 7 is a circuit diagram of an input section of a seventh embodiment of the frequency synthesizer of the present invention.

FIG. 8 is a block configuration diagram of an eighth embodiment of the frequency synthesizer of the present invention.

FIG. 9 is a configuration example of inverter circuits 34 to 38 having different input threshold levels.

FIG. 10 is a block diagram of a ninth embodiment of the frequency synthesizer of the present invention.

FIG. 11 is a block configuration diagram of a tenth embodiment of the frequency synthesizer of the present invention.

FIG. 12 is a connection diagram of the first embodiment of the connection method between the frequency synthesizer and the TCXO of the present invention.

FIG. 13 is a connection diagram of a second embodiment of the connection method between the frequency synthesizer and the TCXO of the present invention.

FIG. 14 is a connection diagram of a third embodiment of the connection method between the frequency synthesizer and the TCXO of the present invention.

FIG. 15 is a connection diagram of a fourth embodiment of the connection method between the frequency synthesizer and the TCXO of the present invention.

FIG. 16 is a block configuration diagram according to an embodiment of a communication device of the present invention.

FIG. 17 is a block diagram of a conventional frequency synthesizer.

FIG. 18 is an example of a reference oscillation input waveform (in the case of a capacitive load) and an output waveform of the waveform shaping circuit 2 in the conventional frequency synthesizer.

FIG. 19 is an example of a reference oscillation input waveform (in the case of inductive load) and an output waveform of the waveform shaping circuit 2 in the conventional frequency synthesizer.

[Explanation of symbols]

10 to 22, 30, 40, 50, 60 Frequency synthesizer CMP comparison circuit 32 of the present invention 32 Waveform shaping circuit 34 Inverter circuit (high threshold level) 36 Inverter circuit (medium threshold level) 38 Inverter circuit (low threshold level) 42 Switching circuit 44 to 48 AND circuits S1 to S3 Control input terminal 52 Serial-parallel converter 62 TCXO

Claims (15)

[Claims] 1. An input circuit for inputting a reference oscillation input signal from a reference signal oscillator to generate a signal for phase comparison, a voltage controlled oscillator for generating a signal of a desired frequency, and an output of the voltage controlled oscillator. A frequency divider, a phase comparison circuit for comparing the phases of the output of the input circuit and the output of the frequency divider, and a control signal of the voltage controlled oscillator for suppressing high frequency components from the output of the phase comparator. In a frequency synthesizer that generates a low-pass filter and that generates a signal of a desired frequency that is synchronized with the reference oscillation input signal, a threshold level changing unit that changes a threshold level when the reference oscillation input signal is input is provided. A frequency synthesizer characterized by the above. 2. The threshold level changing means is P
2. The frequency according to claim 1, wherein the channel field effect transistor and the N channel field effect transistor are complementarily connected to a power source and ground, and the inverter field effect transistor includes a plurality of one field effect transistor connected in parallel. Synthesizer. 3. The threshold level changing means is P
The channel field-effect transistor and the N-channel field-effect transistor are connected complementarily to a power source and ground, and the field-effect transistor includes an inverter circuit in which a plurality of field-effect transistors are connected in series. The frequency synthesizer described in. 4. The threshold level changing means is P
An inverter for connecting a channel field effect transistor and an N channel field effect transistor complementarily to a power supply and a ground, and providing a difference in the gate length of one field effect transistor and the gate length of the other field effect transistor. The frequency synthesizer according to any one of claims 1 to 3, which includes a circuit. 5. The threshold level changing means is P
An inverter for connecting a channel field effect transistor and an N channel field effect transistor complementarily to a power supply and a ground, and providing a difference in the gate width of one field effect transistor and the gate width of the other field effect transistor. The frequency synthesizer according to any one of claims 1 to 4, which comprises a circuit. 6. The frequency synthesizer according to claim 1, wherein the threshold level changing means includes a comparison circuit for comparing the reference oscillation input signal with a reference voltage. 7. The frequency synthesizer according to claim 6, wherein the threshold level changing means includes a reference voltage input terminal, and the voltage of the reference voltage input terminal is the reference voltage. 8. The frequency synthesizer according to claim 1, wherein the input circuit includes a plurality of inverter circuits having different threshold levels. 9. The input circuit comprises a control input terminal,
9. A switching means for switching which of a plurality of inverter circuits having different threshold levels is to be used according to the logic level of the control input terminal.
The frequency synthesizer described in. 10. A serial-parallel conversion circuit and a serial data input terminal for setting a frequency division ratio of the frequency divider, further comprising: setting a frequency division ratio of the frequency divider by a signal from the serial data input terminal. 9. The frequency synthesizer according to claim 8, wherein the input circuit is configured to generate a signal of a desired frequency, wherein the input circuit selects one of a plurality of inverter circuits having different threshold levels according to input data from the serial data input terminal. A frequency synthesizer including switching means for switching whether to use. 11. A method of connecting the reference signal oscillator with a frequency synthesizer which receives a reference oscillation input signal from a reference signal oscillator and generates a signal of a desired frequency in synchronization with the reference oscillation input signal. A method of connecting the frequency synthesizer and the reference signal oscillator, the method including providing a potential difference between the ground potential of the input circuit of the frequency synthesizer and the ground potential of the output circuit of the reference signal oscillator. 12. A method of connecting the reference signal oscillator to a frequency synthesizer which receives a reference oscillation input signal from a reference signal oscillator and generates a signal of a desired frequency in synchronization with the reference oscillation input signal. A method of connecting the frequency synthesizer and the reference signal oscillator, comprising a method of providing a potential difference between the power supply potential of the input circuit of the frequency synthesizer and the power supply potential of the output circuit of the reference signal oscillator. 13. The method according to claim 11 or 12, wherein the method of providing the potential difference uses a constant voltage element.
A method of connecting the frequency synthesizer and the reference signal oscillator according to the above 1. 14. A communication device using the frequency synthesizer according to any one of claims 1 to 10. 15. A communication device using the method for connecting a frequency synthesizer and a reference signal oscillator according to any one of claims 11 to 13.