JPH0773671A - Leakage antenna - Google Patents

Abstract

PURPOSE:To obtain buffer operation adapting to an operational source voltage different from each other by providing a level conversion control part adjusting a circuit threshold value voltage of an amplifier inverter and impressing a prescribed signal to the input. CONSTITUTION:By a sense amplifier 30, a signal MO outputted from a memory cell 18 is compared with a reference voltage Vref, and a sense signal SO is outputted. The amplifier inverter 17 is constituted of a PchFET 1 and an NchFET 2, and the signal YOS of H or L between the source voltage and the grounded voltage is outputted according to the sense signal SO received with the gates of both FETs. By the level conversion control part 31, a gate signal VSO is sent to the PchFET 6 according to the level of the signal VS of the input 32, and the PchFET 6 is operated in parallel to the FET 1 or turned off. Thus, when the voltage of the operational source 3 is e.g. 3V or 5V, the circuit threshold value voltage of the inverter 17 is adapted to the source voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit memory.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example. The signal MO output from the memory cell 26 outputs a reference voltage Vref determined by the balance between the output of the memory and the sense amplifier from the reference voltage generation circuit 27, and the signal MO is higher than the reference voltage Vref by the sense amplifier 28. If it is a potential or a low potential, the level of the sense amplifier output signal SO is inverted and a low potential or high potential signal is output. S
Inverter 2 for amplification determined by the signal level of O
A low-potential or high-potential signal is output by the PchFET 20 and the NchFET 21 and is output by the PchFET 20 at the H level or the NchFET 21 at the L level. Here, the current control NchFET 22
Is an FET provided to prevent a through current with respect to the SO signal output. 29 is an output buffer circuit.

For example, in a conventional circuit, the power supply wiring path 23 is 3 V and the ground wiring path 24 is GND in each circuit.
When the balance adjustment of each FET is performed, the individual output signals are as described above as shown in FIG. 3, and the balanced output signal YO is output.

[0004]

In recent years, along with the development of device processing technology, the technology such as miniaturization, high integration, low power consumption has been remarkably developed, so that the power supply voltage to be used tends to decrease. At present, there is a situation in which the power supply voltage currently used and the power supply voltage of a low voltage accompanying the development are mixed. Even within the integrated circuit, it is necessary to select a logical threshold level that meets these needs.

On the other hand, when the power supply wiring line 23 is set from 3V to 5V under the same conditions of FIG. 2, the circuit threshold voltage of the amplification inverter 25 immediately after the sense amplifier differs depending on the power supply voltage, so that the amplification inverter is 3V. 25, the amplitude of the output of the sense amplifier does not reach the circuit threshold voltage of the amplification inverter 25, and as shown in FIG. 4, the YO output level does not rise to the logic level and remains at the L level. turn into.

Therefore, an object of the present invention is to provide a memory which can be stably operated in a wide power supply voltage range in order to solve the above problems.

[0007]

A first-stage buffer for comparing a signal output from a memory with a reference voltage output from a reference voltage generating circuit by a sense amplifier and amplifying the output signal of the sense amplifier output. At PchFET, the output signal of the sense amplifier is used as the direct input signal
And NchFET, external input terminal, PchFET, N
A PchFET controlled by a two-stage inverter composed of a chFET, a transfer gate composed of an NchFET, and a pull-up PchFET, and the output of the sense amplifier is connected to the input part of the transfer gate. A PchFET that receives the output signal of the level conversion control unit whose output is connected to the output of the PchFET for pull-up, and changes the input level of the external input terminal according to the change of the operating power supply voltage. By selecting whether to input the output signal of the sense amplifier or the level clipped signal to the input, the PchFET and N
The circuit threshold voltage can be adjusted by changing the ratio of the gate width of the chFET, and stable operation in a wide operating range of the power supply voltage can solve the above problems.

Further, in the first stage buffer for comparing the signal output from the memory with the reference voltage output from the reference voltage generating circuit by the sense amplifier and amplifying the output signal of the output sense amplifier, the sense amplifier is used. PchFET and Nch whose output signal is directly input signal
FET, external input terminal, PchFET, NchFET
PchFE controlled by an inverter composed of
It is composed of a transfer gate composed of T and NchFETs and a pulldown NchFET. The output of the sense amplifier is connected to the input part of the transfer gate, and the output of the transfer gate is pulled down by the NchFE.
It is composed of an NchFET that receives the output signal of the level conversion control unit connected to the output of T, and changes the input level of the external input terminal according to the change of the operating power supply voltage. The circuit threshold voltage can be adjusted by changing the ratio of the gate widths of the PchFET and NchFET by selecting whether to input the output signal or the level clipped signal, and stable operation in a wide power supply voltage operating range is possible. By doing so, the above-mentioned problems are solved.

[0009]

Since the threshold level of the signal output from the sense amplifier depends on the ratio of the power supply voltage to the gate width of the FET,
By providing a control terminal from the outside, even if the power supply voltage is used at different power supply voltage values, the logic threshold level can be easily set by the signal from the control terminal. Even if the operating power supply voltage is changed, stable operation can be achieved by changing the logic threshold level.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment according to the present invention.

This circuit has a level conversion control unit 31 for adjusting the circuit threshold voltage of the inverter immediately after the sense amplifier at the time of low voltage operation and the normal operation power supply voltage, and the signal output from the memory cell 18 and the reference. It is composed of a sense amplifier 30 for comparing voltages and an output section 33 taking the above configuration into consideration.

As an example, the amplifying inverter 17 immediately after the sense amplifier serves as an amplifying inverter during low voltage operation.
The ratio of the gate widths of the chFET1 and the NchFET2 is set to 3V, and the above PchFE is set at the normal operating power supply voltage.
PchFE provided to supplement T1 and NchFET2
A memory circuit in which the circuit threshold voltage of the amplification inverter is changed by T6 and which can be similarly used even at 5V will be described below. The ground wiring path 4 is GND, and the power supply wiring path 3 is the power supply voltage at each operation.

The circuit threshold voltage is PchFET and Nc.
It depends on the resistance ratio of the on-state of the hFET, and by increasing the gate width, the on-state resistance value of each FET decreases, and by decreasing the gate width, the on-state resistance value increases. Also, the resistance value of each FET is affected by changing the power supply voltage. Therefore, the circuit threshold voltage can be corrected by correcting the amount of change in the resistance value of each FET according to the gate width ratio.

In the level conversion control unit 31 shown in FIG. 1, when the VS terminal 32 which is an external input terminal is used to select the above-mentioned two types of power source voltages and the VS terminal at 3V is set to the L level, the PchFET 7 and the NchFET 8 are provided. The output of the inverter 9 composed of
The output level of the inverter 12 composed of the PchFET 10 and the NchFET 11 becomes the L level.
Due to this relationship, PchFET 13 and NchFET
The transfer gate 15 constituted by 14 is closed, and the VSO signal is at the H level by the pull-up PchFET 16 connecting the output of the inverter 12 to the gate because the output of the inverter 12 is at the L level. Then, the PchFET 6 which assists the amplification inverter 17 is turned off. Therefore, the threshold voltage of the amplification inverter circuit is PchFET1 and NchF.
It is set for 3V by the gate width ratio of ET2.

Output signal M output from memory cell 18
O is a reference voltage Vref output from the reference voltage generation circuit 19 determined by the balance of the sense amplifier 30.
The signal SO output as an inverted potential by the sense amplifier 30 is compared with the sense amplifier 30, and the transfer gate 15 is closed.
An H-level signal and an L-level signal are output to YOS by the amplification inverter constituted by the chFET2, and the waveforms shown in FIG. 5 are obtained as in FIG. 3, and output to OUTS by the output buffer circuit 34.

On the other hand, considering the case where the VS terminal 32 at 5 V is at H level, the output of the inverter 9 is at L level,
Since the output of the inverter 12 becomes H level, the transfer gate 15 is in the released state, and the output of the inverter 12 is H level, the pull-up PchF is used.
Since the ET 16 is turned off, the VSO signal becomes the output signal SO of the sense amplifier 30. As described above, since the amplification inverter 17 immediately after the sense amplifier balances each FET with the low voltage power supply voltage (3V in this case), the output signal MO of the memory cell 18 and the reference voltage Vref are at 3V. Since the potential is higher than that of the sense amplifier, the output SO of the sense amplifier is output as shown in FIG. 4. However, since the transfer gate 15 is in the released state, the PchFET 6 is turned on or off depending on the output signal of the sense amplifier. . The inverter 17 has a Pc
The circuit threshold voltage is determined by the ratio of the gate widths of hFET6, PchFET1 and NchFET2.
Since chFET6 and PchFET1 are in parallel,
Since the ON resistance of the PchFET decreases, the circuit threshold voltage rises, and YOS becomes a signal obtained by inverting and amplifying the signal of SO similarly to the operation at 3V, and is input to the output buffer circuit 34, and the L level is output by the output buffer circuit. , H level full-swing signal is output to OUTS, so that it is output as shown in FIG. 6 instead of OUT shown in FIG. Further, for 5V operation, an amplification inverter (PchFET1 and NchFET immediately after the sense amplifier
Even if the gate width ratio of 2) is set, the same operation can be performed by rebalancing the gate width ratio of the amplifying inverter at 3V in the same manner. FIG. 7 is a diagram showing another embodiment according to the present invention.

This circuit has a level conversion control unit 31 for adjusting the circuit threshold voltage of the inverter immediately after the sense amplifier at the time of low voltage operation and the normal operation power supply voltage, and the signal output from the memory cell 18 and the reference. It is composed of a sense amplifier 30 for comparing voltages and an output section 33 taking the above configuration into consideration.

As an example, the amplification inverter 17 immediately after the sense amplifier has a gate width ratio of 5V of PchFET1 and NchFET2, which serves as an amplification inverter during normal voltage operation.
For PchFET1 in low voltage operation
And NchFET provided to supplement NchFET2
The memory circuit which can be similarly used at 3V by changing the circuit threshold voltage of the amplification inverter by 6'will be described below. The ground wiring path 4 is GND, and the power supply wiring path 3 is the power supply voltage at each operation.

The circuit threshold voltage is PchFET and Nc.
It depends on the resistance ratio of the on-state of the hFET, and by increasing the gate width, the on-state resistance value of each FET decreases, and by decreasing the gate width, the on-state resistance value increases. Also, the resistance value of each FET is affected by changing the power supply voltage. Therefore, the circuit threshold voltage can be corrected by correcting the amount of change in the resistance value of each FET according to the gate width ratio.

In the level conversion control section 31 shown in FIG. 7, when the VS terminal 32 which is an external input terminal is used to select the above-mentioned two types of power supply voltages and the VS terminal at 5V is set to the H level, the PchFET 7 and the NchFET 8 are provided. The output of the inverter 9 constituted by the L level becomes L level.
Due to this relationship, PchFET 13 and NchFET
The transfer gate 15 constituted by 14 is closed, and the signal of VSO is in the L level by the pull-down NchFET 16 'connecting the VS terminal to the gate because the VS terminal is in the H level.
The NchFET 6'which assists the amplification inverter 17 is turned off. Therefore, the circuit threshold voltage of the amplification inverter is set for 5V by the ratio of the gate widths of PchFET1 and NchFET2.

Output signal M output from memory cell 18
O is a reference voltage Vref output from the reference voltage generation circuit 19 determined by the balance of the sense amplifier 30.
The signal SO output as an inverted potential by the sense amplifier 30 is compared with the sense amplifier 30, and the transfer gate 15 is closed.
The amplifying inverter configured by the chFET 2 outputs the H level signal and the L level signal to YOS, and the output buffer circuit 34 outputs them to OUTS.

On the other hand, considering the case where the VS terminal 32 at 3V is at L level, the output of the inverter 9 becomes H level, the transfer gate 15 is in the released state, and the VS terminal is at L level. Since the pull-down NchFET 16 'is turned off, the VSO signal becomes SO which is the output signal of the sense amplifier 30.
As described above, since the amplification inverter 17 immediately after the sense amplifier balances each FET with the normal power supply voltage (5V in this case), the output signal M of the memory cell 18 is
O and the reference voltage Vref are lower in potential than 5 V, but since the transfer gate 15 is in the released state, the NchFET 6'is turned on or off by the output signal of the sense amplifier. The inverter 17 has N
chFET6 ', PchFET1 and NchFET2
The circuit threshold voltage is determined by the ratio of the gate width of the NchFET 6'and the NchFET 2 in parallel at this time, the on-resistance of the NchFET is lowered, the circuit threshold voltage is lowered, and YOS is the same as that of the operation at 5V. The signal becomes a signal obtained by inverting and amplifying the signal, and is input to the output buffer circuit 34, and the output buffer circuit outputs a full-swing signal of L level and H level to OUTS.
Even if the ratio of the gate widths of the amplification inverters (PchFET1 and NchFET2) immediately after the sense amplifier is set for 3V operation, by rebalancing the ratio of the gate widths of the amplification inverters at 5V in the same manner. ,
It is possible to perform the same operation.

[0024]

According to the present invention, the VS terminal which is the external terminal is provided as described above, and the level conversion control circuit section is controlled to operate by adjusting the logical threshold value at different power supply voltages. It will be possible. Also,
By changing the size of the logic threshold conversion PchFET or NchFET, a wide range of power supply voltage operations can be performed. Further, even if the operating power supply voltage of the integrated circuit including the present invention is lowered or increased in the future, it can be used as it is by converting the power supply wiring path and the logic threshold value.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of a memory circuit showing an embodiment of the present invention.

FIG. 2 is an electric circuit diagram of a conventional memory circuit.

FIG. 3 is a waveform diagram during 3V operation in a conventional example.

FIG. 4 is a waveform diagram at the time of 5 V operation in the conventional example.

FIG. 5 is a waveform diagram at the time of 3V operation in the present invention.

FIG. 6 is a waveform diagram during 5 V operation in the present invention.

FIG. 7 is an electric circuit diagram of a memory circuit showing another embodiment of the present invention.

[Explanation of symbols]

 1 PchFET 2 NchFET 3 Power supply wiring path 4 Ground wiring path 5 NchFET 6 for current control PchFET for logical threshold conversion 6'NchFET for logical threshold conversion 7, 10 PchFET 8, 11 NchFET 9, 12 Inverter 15 Transfer gate 16 PchFET for pull-up 16 ′ Pull-down NchFET 17 Amplification inverter 18 Memory cell 19 Reference voltage generation circuit 30 Sense amplifier 31 Level conversion control section 32 VS terminal 33 Output section 34 Output buffer circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 8321-5J H03K 19/00 101 K

Claims (2)

[Claims] 1. A sense amplifier in a first stage buffer for comparing a signal output from a memory with a reference voltage output from a reference voltage generation circuit by a sense amplifier and amplifying an output signal of the sense amplifier output. PchFET and NchFE whose output signal is directly input signal
PchFE controlled by a two-stage inverter composed of T, an external input terminal, PchFET, and NchFET
It is composed of a transfer gate composed of T and Nch FETs and a pull-up Pch FET, the output of the sense amplifier is connected to the input part of the transfer gate, and the output of the transfer gate is connected to the pull-up PchFE.
It is composed of a PchFET which receives the output signal of the level conversion control unit connected to the output of T, and changes the input level of the external input terminal according to the change of the operating power supply voltage. A buffer circuit characterized in that the circuit threshold voltage can be adjusted by changing the gate width ratio of the PchFET and the NchFET by selecting whether to input the output signal or the level-clip signal. . 2. A sense amplifier in a first stage buffer for comparing a signal output from a memory with a reference voltage output from a reference voltage generating circuit by a sense amplifier and amplifying an output signal of the sense amplifier output. PchFET and NchFE whose output signal is directly input signal
T, PchFET, N controlled by an inverter composed of an external input terminal and PchFET, NchFET
The level conversion control unit is composed of a transfer gate composed of a chFET and a pull-down NchFET, the output of the sense amplifier is connected to the input of the transfer gate, and the output of the transfer gate is connected to the output of the pull-down NchFET. An NchFET that receives the output signal as an input, and by changing the input level of the external input terminal according to the change of the operating power supply voltage, the output signal of the sense amplifier is input to the input of the NchFET, or the level clipped signal. The buffer circuit is characterized in that the circuit threshold voltage can be adjusted by changing the gate width ratio of the PchFET and the NchFET by selecting whether to input.