JPH02146815A - Input circuit for semiconductor integrated circuit - Google Patents
Input circuit for semiconductor integrated circuitInfo
- Publication number
- JPH02146815A JPH02146815A JP63301427A JP30142788A JPH02146815A JP H02146815 A JPH02146815 A JP H02146815A JP 63301427 A JP63301427 A JP 63301427A JP 30142788 A JP30142788 A JP 30142788A JP H02146815 A JPH02146815 A JP H02146815A
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- circuit
- input
- inverters
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000010586 diagram Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 2
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路の入力回路に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input circuit for a semiconductor integrated circuit.
第３図は従来の半導体集積回路の入力回路のブロック図
で、入力回路は外部端子（１３、インバータ［１３、お
よび内部回路１１４１から成っている。第４図は第３図
の外部端子ｕｚに入る電気信号の波形図である。外部端
子（Ｉ７Ｊから入った電気信号０９はインバータα３の
持つしきい値によりＢ又は乙の出力に変換され、内部回
路α滲へ出力される。第４図はこの様子を示しておジ、
仮にインバータ０のしきい値をＱ、 ５ ＶＤＤとする
と、入力信号α９がインバータ０のしきい値であるＱ、
５ ＶＤＤより大きいとき、インバータ０はＨを出力
し、しきい値より小さいとき、インバータｌ１３ｔｌｉ
Ｌを出力する。FIG. 3 is a block diagram of the input circuit of a conventional semiconductor integrated circuit, and the input circuit consists of an external terminal (13), an inverter [13, and an internal circuit 1141. It is a waveform diagram of an input electric signal.The electric signal 09 input from the external terminal (I7J) is converted into the output of B or B by the threshold value of the inverter α3, and is output to the internal circuit α. Please show me this situation.
If the threshold of inverter 0 is Q, 5 VDD, input signal α9 is the threshold of inverter 0, Q,
When it is larger than 5 VDD, inverter 0 outputs H, and when it is smaller than the threshold, inverter l13tli
Output L.
次に従来の例としてＯＲを用いたリセット回路の動作に
ついて説明する。コンデンサＣに充電された電荷バイパ
スコンデンサなどのために電池交換の際に放電し切らな
いものとする。そのときのＯＲコンデンサの端子電圧が
リセット回路のしきい値電圧より高いと、電池交換をし
たにもかかわらずリセット信号の発生が行なわれない。Next, the operation of a reset circuit using OR will be described as a conventional example. It is assumed that the capacitor C is not fully discharged when replacing the battery due to the charge charged in the bypass capacitor or the like. If the terminal voltage of the OR capacitor at that time is higher than the threshold voltage of the reset circuit, no reset signal is generated even though the battery has been replaced.
逆に。vice versa.
しきい値電圧が高いとバッテリバックアップなどのアプ
リケーションでは電圧の低くなったバッテリから商用電
源による電源（一般にバックアップ用バッテリの電圧よ
りも高い）に切換わるとき。When the threshold voltage is high, in applications such as battery backup, when switching from a low voltage battery to a commercial power source (generally higher than the backup battery voltage).
リセットがかかつてしまう。It takes a long time to reset.
従来のインバータは以上のように構成されていたので、
インバータのしきい値を変更したい場合インバータのし
きい値は固定されているため変更することができないと
いう課題があった。Conventional inverters were configured as described above, so
There is a problem in that when it is desired to change the threshold value of the inverter, the threshold value of the inverter is fixed and cannot be changed.
この発明は上記のような課題を解決するためになされた
もので、それぞれしきい値の異なるインバータを複数個
使用することによってインバータのしきい値の変更を可
能とすることを目的とする。This invention was made to solve the above-mentioned problems, and it is an object of the present invention to make it possible to change the threshold value of an inverter by using a plurality of inverters each having a different threshold value.
この発明に係る半導体集積回路の入力回路はそれぞれし
きい値の異なるインバータを複数個用いて、その出力を
切換える選択回路を設けたものである。The input circuit of the semiconductor integrated circuit according to the present invention uses a plurality of inverters each having a different threshold value, and is provided with a selection circuit for switching the outputs of the inverters.
この発明に係る半導体集積回路の入力回路はそれぞれし
きい値の異なる複数個のインバータを切換えるようにし
たので、インバータのしきい値を任意に変更することが
できる。Since the input circuit of the semiconductor integrated circuit according to the present invention switches a plurality of inverters each having a different threshold value, the threshold value of the inverter can be changed arbitrarily.
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例の半導体集積回路の入力回路の
ブロック図を示す。入力回路の構成は外部端子（１）、
それぞれしきい値の違うインバータ群（２）（図の場合
は３個のインバータ（インバータ１ （８１、インバー
タ２（４）、インバータ３ （５） ）使用している。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a block diagram of an input circuit of a semiconductor integrated circuit according to an embodiment of the present invention. The input circuit consists of external terminals (1),
Inverter group (2) (in the case of the figure, three inverters (inverter 1 (81), inverter 2 (4), inverter 3 (5)) are used, each having a different threshold value.
）このインバータ群（２）の出力を切換える選択回路（
６）及びその出力を受ける内部回路（γ）から成る。第
２図は第１図の外部端子（１）に入力された電気信号（
８）とその入力された電気信号に対する各インバータの
出力（９）、α〔及びαυの波形図を示している。) A selection circuit (
6) and an internal circuit (γ) that receives its output. Figure 2 shows the electrical signal input to the external terminal (1) in Figure 1 (
8) and the output (9) of each inverter in response to the input electrical signal, α[, and αυ waveform diagrams are shown.
第１図において、インバータ１（８）の出力を選択回路
（６）により選択した場合、第２図（９）の出力が得ら
れる。これはインバータ１（８）はしきい値が０．５ｖ
ＤＤであるため、入力信号が０．５ｖＤＤよシ大きいと
きＨを出力して、０．５ ＶＤＤよシ小さいときＬを出
力しているためである。同様な理由でしきい値がＱ、
４ Ｖｏｏであるインバータ２（４）を選択した場合は
第２図（至）の出力が得られ、しきい値がＱ、 ３ Ｖ
ｏ。In FIG. 1, when the output of inverter 1 (8) is selected by the selection circuit (6), the output shown in FIG. 2 (9) is obtained. This means that inverter 1 (8) has a threshold of 0.5v.
This is because since it is a DD, it outputs H when the input signal is greater than 0.5 VDD, and outputs L when it is smaller than 0.5 VDD. For the same reason, the threshold value is Q,
If inverter 2 (4) with 4 Voo is selected, the output shown in Fig. 2 (to) is obtained, and the threshold value is Q, 3 V
o.
であるインバータ３（６）を選択した場合は第２図０υ
の出力が得られる。If inverter 3 (6) is selected, then 0υ in Figure 2
The output is obtained.
選択回路（６）には第１図のようにトランスミッション
ゲートを用いたものなどがある。そしてこの実施例では
トランスミッションゲートの選択信号Ｓ！、 ８２ 、
Ｓｇによってインバータの出力を選択できる。The selection circuit (6) includes one using a transmission gate as shown in FIG. In this embodiment, the transmission gate selection signal S! , 82,
The output of the inverter can be selected by Sg.
以上のようにこの発明によればそれぞれしきい値の違う
インパータを複数個設け、その出力の切換えを可能とす
ることによりインバータのしきい値を任意に変更するこ
とができる。As described above, according to the present invention, by providing a plurality of inverters each having a different threshold value and making it possible to switch their outputs, the threshold value of the inverter can be arbitrarily changed.
第１図はこの発明の一実施例を示す半導体集積回路の入
力回路のブロック図、第２図は第１図の入力信号と出力
信号の関係を示す波形図、第３図は従来の半導体集積回
路の入力回路のブロック図、第４図は第１図の入力信号
と出力信号の関係を示す波形図である。
図において、（１）は外部端子、（２）はインバータ群
、（８）（４）（６）はインバータ、（６）は選択回路
、（７）は内部回路を示す。
４；４〕ハ゛−′ｉ；ｌ
第１図
第３図
２１発明の名称
半導体集積回路の入力回路
３、補正をする者
代表者 志
岐
守
哉
５、補正の対象
明細書の発明の詳細な説明の欄。
６、補正の内容
（１）明細書の第２頁第８行から第９行に「充電された
電荷バイパスコンデンサ」とあるのを「充電された電荷
がバイパスコンデンサ」に訂正する。
以上Fig. 1 is a block diagram of an input circuit of a semiconductor integrated circuit showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing the relationship between the input signal and output signal of Fig. 1, and Fig. 3 is a conventional semiconductor integrated circuit. FIG. 4, which is a block diagram of the input circuit of the circuit, is a waveform diagram showing the relationship between the input signal and output signal of FIG. 1. In the figure, (1) shows an external terminal, (2) an inverter group, (8), (4), and (6) inverters, (6) a selection circuit, and (7) an internal circuit. 4;4]Ha-'i;l Figure 1 Figure 3 Figure 21 Name of the invention Input circuit for semiconductor integrated circuit 3 Representative of the person making the amendment Moriya Shiki 5 Detailed description of the invention in the specification to be amended column. 6. Details of the amendment (1) In lines 8 to 9 of page 2 of the specification, the phrase "charged charge bypass capacitor" is corrected to "the charged charge is a bypass capacitor."that's all
Claims (1)
電気信号に対しそれぞれしきい値の異なる複数のインバ
ータと、このインバータの入力又は出力を選択できる選
択回路とを備えたことを特徴とする半導体集積回路の入
力回路。An input circuit for a semiconductor integrated circuit, comprising a plurality of inverters each having a different threshold value for an electric signal input from an external terminal, and a selection circuit that can select the input or output of the inverter. input circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63301427A JPH02146815A (en) | 1988-11-28 | 1988-11-28 | Input circuit for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63301427A JPH02146815A (en) | 1988-11-28 | 1988-11-28 | Input circuit for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02146815A true JPH02146815A (en) | 1990-06-06 |
Family
ID=17896750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63301427A Pending JPH02146815A (en) | 1988-11-28 | 1988-11-28 | Input circuit for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02146815A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0525840U (en) * | 1991-09-12 | 1993-04-02 | 日本電気株式会社 | Input circuit of integrated circuit |
| WO1998047230A1 (en) * | 1997-04-11 | 1998-10-22 | Xilinx, Inc. | Input/output buffer supporting multiple i/o standards |
| US5877632A (en) * | 1997-04-11 | 1999-03-02 | Xilinx, Inc. | FPGA with a plurality of I/O voltage levels |
| US5991908A (en) * | 1997-09-29 | 1999-11-23 | Xilinx, Inc. | Boundary scan chain with dedicated programmable routing |
| US6071314A (en) * | 1997-09-29 | 2000-06-06 | Xilinx, Inc. | Programmable I/O cell with dual boundary scan |
| US6120551A (en) * | 1997-09-29 | 2000-09-19 | Xilinx, Inc. | Hardwire logic device emulating an FPGA |
| JP2003037499A (en) * | 2001-07-23 | 2003-02-07 | Murata Mfg Co Ltd | Frequency synthesizer, connection method between reference signal oscillator and frequency synthesizer, and communication device employing them |
| US6625788B1 (en) | 1998-06-26 | 2003-09-23 | Xilinx, Inc. | Method for verifying timing in a hard-wired IC device modeled from an FPGA |
| US7345567B2 (en) | 2004-12-02 | 2008-03-18 | Fdk Corporation | Inverter transformer |
| JP2010057068A (en) * | 2008-08-29 | 2010-03-11 | Kyocera Kinseki Corp | Oscillator |
-
1988
- 1988-11-28 JP JP63301427A patent/JPH02146815A/en active Pending
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0525840U (en) * | 1991-09-12 | 1993-04-02 | 日本電気株式会社 | Input circuit of integrated circuit |
| WO1998047230A1 (en) * | 1997-04-11 | 1998-10-22 | Xilinx, Inc. | Input/output buffer supporting multiple i/o standards |
| US5877632A (en) * | 1997-04-11 | 1999-03-02 | Xilinx, Inc. | FPGA with a plurality of I/O voltage levels |
| US5958026A (en) * | 1997-04-11 | 1999-09-28 | Xilinx, Inc. | Input/output buffer supporting multiple I/O standards |
| US6448809B2 (en) | 1997-04-11 | 2002-09-10 | Xilinx, Inc. | FPGA with a plurality of input reference voltage levels |
| US6049227A (en) * | 1997-04-11 | 2000-04-11 | Xilinx, Inc. | FPGA with a plurality of I/O voltage levels |
| US6294930B1 (en) | 1997-04-11 | 2001-09-25 | Xilinx, Inc. | FPGA with a plurality of input reference voltage levels |
| US6204691B1 (en) | 1997-04-11 | 2001-03-20 | Xilinx, Inc. | FPGA with a plurality of input reference voltage levels grouped into sets |
| US6134517A (en) * | 1997-09-29 | 2000-10-17 | Xilinx, Inc. | Method of implementing a boundary scan chain |
| US6120551A (en) * | 1997-09-29 | 2000-09-19 | Xilinx, Inc. | Hardwire logic device emulating an FPGA |
| US6226779B1 (en) | 1997-09-29 | 2001-05-01 | Xilinx, Inc. | Programmable IC with gate array core and boundary scan capability |
| US6071314A (en) * | 1997-09-29 | 2000-06-06 | Xilinx, Inc. | Programmable I/O cell with dual boundary scan |
| US6353921B1 (en) | 1997-09-29 | 2002-03-05 | Xilinx, Inc. | Hardwire logic device emulating any of two or more FPGAs |
| US5991908A (en) * | 1997-09-29 | 1999-11-23 | Xilinx, Inc. | Boundary scan chain with dedicated programmable routing |
| US6625788B1 (en) | 1998-06-26 | 2003-09-23 | Xilinx, Inc. | Method for verifying timing in a hard-wired IC device modeled from an FPGA |
| JP2003037499A (en) * | 2001-07-23 | 2003-02-07 | Murata Mfg Co Ltd | Frequency synthesizer, connection method between reference signal oscillator and frequency synthesizer, and communication device employing them |
| US7345567B2 (en) | 2004-12-02 | 2008-03-18 | Fdk Corporation | Inverter transformer |
| JP2010057068A (en) * | 2008-08-29 | 2010-03-11 | Kyocera Kinseki Corp | Oscillator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5095223A (en) | Dc/dc voltage multiplier with selective charge/discharge | |
| JPH0119298B2 (en) | ||
| US5463542A (en) | DC/DC converter and RS-232 interface circuit using the same | |
| JPH09312968A (en) | Charge pump circuit | |
| JPH02146815A (en) | Input circuit for semiconductor integrated circuit | |
| JPH02125518A (en) | Semiconductor integrated circuit | |
| US5644259A (en) | Reset circuit and integrated circuit including the same | |
| JP2886281B2 (en) | Boost circuit | |
| JPS61129916A (en) | Delay circuit | |
| JPH04117716A (en) | Output circuit | |
| JP3096711B2 (en) | Output voltage control device for charge pump | |
| JPH11299226A (en) | Dc voltage converter | |
| JPS61109312A (en) | Signal delay circuit | |
| US6369587B1 (en) | Pulse center detection circuit | |
| JPH0491656A (en) | Booster circuit | |
| JPS62144565A (en) | Booster circuit | |
| SU951592A1 (en) | Stabilized step-down ac converter | |
| JPH02233014A (en) | Positive/negative signal generating circuit | |
| JPS6372217A (en) | Control signal generating circuit | |
| JPS6334953A (en) | Semiconductor integrated circuit | |
| JPH0595669A (en) | Voltage converter | |
| JPH02301320A (en) | Reset circuit | |
| JPH02265314A (en) | Input circuit in semiconductor integrated circuit | |
| JPH02237219A (en) | Output circuit | |
| JPS5948568B2 (en) | flip-flop circuit |