JPS61109312A - Signal delay circuit - Google Patents

Signal delay circuit

Info

Publication number
JPS61109312A
JPS61109312A JP59231925A JP23192584A JPS61109312A JP S61109312 A JPS61109312 A JP S61109312A JP 59231925 A JP59231925 A JP 59231925A JP 23192584 A JP23192584 A JP 23192584A JP S61109312 A JPS61109312 A JP S61109312A
Authority
JP
Japan
Prior art keywords
voltage
power supply
supply voltage
capacitor
lowered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59231925A
Other languages
Japanese (ja)
Inventor
Kenji Mori
Hidekata Asai
Original Assignee
Nec Ic Microcomput Syst Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Ic Microcomput Syst Ltd filed Critical Nec Ic Microcomput Syst Ltd
Priority to JP59231925A priority Critical patent/JPS61109312A/en
Publication of JPS61109312A publication Critical patent/JPS61109312A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a signal delay circuit whose delay time is independent of a voltage fluctuation by utilizing a terminal voltage of a branch circuit in which an active element whose effective resistance value changed depending on a power supply voltage is connected in series with a capacitor as a delay voltage.
CONSTITUTION: Suppose that the power supply voltage is lowered than a normal value, a current flowing a transistor (TR)Q1 is decreased to retard the leading of a capacitor C. When the power supply voltage, however, is decreased, since the effective resistance of a TR Q5 is increased, the increment of the terminal voltage compensates the decrement of the voltage rise of the capacitor C. Thus, the time when the voltage at a node M reaches a threshold value to activate a CMOS inverter 2 of the post-stage is made equal to the time for the normal power supply voltage. On the other hand, when the power supply voltage increases, the leading of the voltage across the capacitor C is quickened, the effective resistance value of the TR Q1 is lowered and its terminal voltage is lowered, resulting that the delay time is finally the same as the case with the normal power supply voltage.
COPYRIGHT: (C)1986,JPO&Japio
JP59231925A 1984-11-02 1984-11-02 Signal delay circuit Pending JPS61109312A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59231925A JPS61109312A (en) 1984-11-02 1984-11-02 Signal delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59231925A JPS61109312A (en) 1984-11-02 1984-11-02 Signal delay circuit

Publications (1)

Publication Number Publication Date
JPS61109312A true JPS61109312A (en) 1986-05-27

Family

ID=16931209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59231925A Pending JPS61109312A (en) 1984-11-02 1984-11-02 Signal delay circuit

Country Status (1)

Country Link
JP (1) JPS61109312A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63217820A (en) * 1987-03-06 1988-09-09 Nec Corp Cmos delay circuit
JPH0478220A (en) * 1990-07-20 1992-03-12 Samsung Electron Co Ltd Signal delaying circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63217820A (en) * 1987-03-06 1988-09-09 Nec Corp Cmos delay circuit
JPH0478220A (en) * 1990-07-20 1992-03-12 Samsung Electron Co Ltd Signal delaying circuit

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