JPH0525840U - Input circuit of integrated circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Match the threshold voltage mismatch without providing a buffer circuit outside. [Structure] An integrated circuit LSI has a plurality of identical circuits mounted therein, and an input circuit (1) 1 has a first buffer circuit 11 and a second buffer circuit 12, and its output signal is selected by a selection circuit 13. There is. That is, the input signal 101 is input to the first buffer circuit 11 and the second buffer circuit 12, and one of its output signals is selected by the selection circuit 13 by the selection signal 103 and input to the internal circuit as the output signal 102. . The threshold voltage of the first buffer circuit 11 is CMOS
The system threshold voltage and the second buffer circuit 12 are set to the TTL system threshold voltage, respectively.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an input circuit of an integrated circuit.

[0002]

[Prior Art]

 Conventionally, the input circuit of this kind of integrated circuit has its own standard as an operating condition for an input signal. For example, the same applies to the threshold voltage (in this case, the limit voltage at which the LOW level of the input signal can be detected). However, the CMOS MOS integrated circuit generally has a threshold voltage higher than that of the TTL system. ing .

[0003]

[Problems to be solved by the device]

 As described above, in the conventional example, since the threshold voltage for the input signal is fixed, there is a problem that a buffer circuit must be additionally provided if this does not match due to the interface with the front-end circuit. An example of this inconsistency is that if an input circuit with a TTL threshold voltage is used for a CMOS level input signal, it can be used in terms of level, but the input signal has a load capacitance, etc. If the trailing edge of the pulse is inclined due to the influence of, the output signal has a problem that the HIGH level time is extended.

[0004]

[Means for Solving the Problems]

 The input circuit of the integrated circuit of the present invention comprises a first buffer circuit having a first threshold voltage for an input signal, and a second buffer circuit having a second threshold voltage for the input signal. A selection circuit for selecting one of the output signals of the first buffer circuit and the second buffer circuit by an external selection signal and inputting the selected output signal to an internal circuit.

[0005]

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the circuit configuration of this embodiment. The integrated circuit LSI has a plurality of identical circuits mounted therein, and the input circuit (1) 1 has a first buffer circuit 11 and a second buffer circuit 12, and an output signal thereof is selected by a selection circuit 13. That is, the input signal 101 is input to the first buffer circuit 11 and the second buffer circuit 12, and any one of its output signals is selected by the selection circuit 13 by the selection signal 103 and input to the internal circuit as the output signal 102. .. The threshold voltage of the first buffer circuit 11 is set to the CMOS threshold voltage, and the second buffer circuit 12 is set to the TTL threshold voltage. The input circuit (2) 2 and below have the same configuration.

FIG. 2 shows a falling waveform when the input signal 101 is off, which is a case where the waveform is inclined due to the influence of load capacitance and the like. Also, the CMOS system threshold voltage and the TTL system threshold voltage are shown in the figure, but points a and b are the respective times from the falling point of the input signal 101 to the detection of the LOW level. Shows. That is, in this case, by selecting the CMOS system threshold voltage side, the extension time of the HIGH level can be shortened from a to b.

[0007]

[Effect of the device]

 As described above, in the present invention, since the threshold voltage can be selected, it is possible to achieve matching with the front-end circuit without separately providing a buffer circuit. Therefore, it has an effect of reducing pulse distortion such as extension of the HIGH level of the input signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of this embodiment.

FIG. 2 is a waveform diagram of an input signal in this embodiment.

[Explanation of symbols]

 1, 2 and 3 input circuit 11 first buffer circuit 12 second buffer circuit 13 selection circuit

Claims (1)

[Scope of utility model registration request] 1. A first buffer circuit having a first threshold voltage for an input signal, a second buffer circuit having a second threshold voltage for the input signal, and the first buffer circuit. An input circuit of an integrated circuit, comprising: a selection circuit for selecting an output signal of either the buffer circuit or the second buffer circuit by a selection signal from the outside and inputting the selection signal to an internal circuit.